Circuit Voltage Probe Based on Time-Integrated Measurements of Optical Emission From Leakage Current

2002 ◽  
Author(s):  
Franco Stellari ◽  
Peilin Song ◽  
James C. Tsang ◽  
Moyra K. McManus ◽  
Mark B. Ketchen
Keyword(s):  
Leakage Current ◽  
Voltage Drop ◽  
Optical Emission ◽  
Channel Length ◽  
Operating Conditions ◽  
Power Circuit ◽  
Hot Carrier ◽  
Optical Inspection ◽  
Low Threshold ◽  
Circuit Power

Abstract Hot-carrier luminescence emission is used to diagnose the cause of excess quiescence current, IDDQ, in a low power circuit implemented in CMOS 7SF technology. We found by optical inspection of the chip that the high IDDQ is related to the low threshold, Vt, device process and in particular to transistors with minimum channel length (0.18 μm). In this paper we will also show that it is possible to gain knowledge regarding the operating conditions of the IC from the analysis of optical emission due to leakage current, aside from simply locating defects and failures. In particular, we will show how it is possible to calculate the voltage drop across the circuit power grid from time-integrated acquisitions of leakage luminescence.

Hot Carrier Effects in Deep Submicron Nmosfets

1996 ◽  
Vol 428 ◽  
Author(s):  
Abhijit Phanse ◽  
Samar Saha
Keyword(s):  
Electric Fields ◽  
Channel Length ◽  
Deep Submicron ◽  
Short Channel ◽  
Hot Carrier ◽  
Velocity Saturation ◽  
Substrate Current ◽  
Hot Carrier Effects ◽  
Saturation Effects ◽  
Channel Lengths

AbstractThis paper addresses hot-carrier related reliability issues in deep submicron silicon nMOSFET devices. In order to monitor the hot-carrier induced device degradation, the substrate current was measured for devices with varying channel lengths (20 um - 0.24 um) under various biasing conditions. Deep submicron devices experience velocity saturation of channel carriers due to extremely high lateral electric fields. To evaluate the effects of velocity saturation in the channel, the pinch-off length in the channel was extracted for all the devices of the target technology. It was observed that for very short channel devices, carriers in most of the channel experience velocity saturation and almost the entire channel gets pinched off. It is shown in this paper that for very short channel devices, the pinch-off length in the channel is limited by the effective channel length, and that velocity saturation effects are critical to the transport of channel carriers.

scholarly journals 3D Double Gate FinFET Construction of 30 nm Technology Node Impact Towards Short Channel Effect

2018 ◽  
Vol 12 (3) ◽  
pp. 1358
Author(s):  
Ameer F. Roslan ◽  
F. Salehuddin ◽  
A.S. M.Zain ◽  
K.E. Kaharudin ◽  
H. Hazura ◽  
...  
Keyword(s):  
Leakage Current ◽  
Electrical Characterization ◽  
Channel Length ◽  
Double Gate ◽  
Short Channel ◽  
3D Design ◽  
Drive Current ◽  
Minimum Requirement ◽  
Technology Roadmap ◽  
Low Performance

<p>This paper presents an investigation on properties of Double Gate FinFET (DGFinFET) and impact of physical properties of FinFET towards short channel effects (SCEs) for 30 nm device, where depletion-layer widths of the source-drain corresponds to the channel length aside from constant fin height (HFIN) and the fin thickness (TFIN). Virtual fabrication process of 3-dimensional (3D) design is applied throughout the study and its electrical characterization is employed and substantial is shown towards the FinFET design whereby in terms of the ratio of drive current against the leakage current (ION/IOFF ratio) at 563138.35 compared to prediction made by the International Technology Roadmap Semiconductor (ITRS) 2013. Conclusively, the incremental in ratio has fulfilled the desired in incremental on the drive current as well as reductions of the leakage current. Threshold voltage (VTH) meanwhile has also achieved the nominal requirement predicted by the International Technology Roadmap Semiconductor (ITRS) 2013 for which is at 0.676±12.7% V. The ION , IOFF and VTH obtained from the device has proved to meet the minimum requirement by ITRS 2013 for low performance Multi-Gate technology.</p>

scholarly journals Mathematical Model of Pressure Formation Process along the Helix Channel Length of Screw Grinder

2020 ◽  
Author(s):  
Valery Pelenko ◽  
Ilkhom Usmanov ◽  
Vyacheslav Pokholchenko ◽  
Irina Smirnova
Keyword(s):  
Energy Consumption ◽  
Mathematical Description ◽  
Analytical Description ◽  
High Energy ◽  
Channel Length ◽  
Operating Conditions ◽  
Technical Equipment ◽  
Mining Equipment ◽  
Technological Parameters ◽  
Total Energy Consumption

The improvement of the technical equipment effectiveness is currently becoming particularly important. This applies not only to large and high-energy-intensive machines, but also to household appliances, the total energy consumption of which often exceeds the energy consumption of the overall equipment. These types of devices include, in particular, grinding and cutting equipment. The mathematical description of the processes carried out on this equipment is generalized and can be extended to a wider class of machines, including waste processing and mining equipment. The technological parameters, the design of screw grinders, and the processes of movement, deformation, extrusion and cutting carried out in them are characterized by a significant number of factors affecting the energy intensity. The main ones are the geometric parameters of the screw, machine’s body, cross knife, grinding plate’s thickness, the number and diameter of holes in it, as well as the product’s physical-mechanical characteristics and operating conditions. The most important for the mathematical description are the zones and processes where the main share of the consumed power is spent. The complexity of their analytical description is due to a simplified consideration of either individual technological zones of grinders’ existing designs, or the use of unreasonable simplifications.

Dependence of hot-carrier immunity on channel length and channel width in MOSFETs with N/sub 2/O-grown gate oxides

1992 ◽  
Vol 13 (12) ◽  
pp. 651-653 ◽  
Author(s):  
G.Q. Lo ◽  
J. Ahn ◽  
D.-L. Kwong ◽  
K.K. Young
Keyword(s):  
Channel Length ◽  
Channel Width ◽  
Gate Oxides ◽  
Hot Carrier

scholarly journals 10 kV Silicon Carbide PiN Diodes—From Design to Packaged Component Characterization

Energies ◽  
2019 ◽  
Vol 12 (23) ◽  
pp. 4566 ◽  
Author(s):  
Asllani ◽  
Morel ◽  
Phung ◽  
Planson
Keyword(s):  
Silicon Carbide ◽  
Leakage Current ◽  
Voltage Drop ◽  
Forward Bias ◽  
Forward Voltage ◽  
Pin Diodes ◽  
Pulse Switching ◽  
Turn On ◽  
Forward Voltage Drop ◽  
Fabrication And Characterization

This paper presents the design, fabrication and characterization results obtained on the last generation (third run) of SiC 10 kV PiN diodes from SuperGrid Institute. In forward bias, the 59 mm2 diodes were tested up to 100 A. These devices withstand voltages up to 12 kV on wafer (before dicing, packaging) and show a low forward voltage drop at 80 A. The influence of the temperature from 25 °C to 125 °C has been assessed and shows that resistivity modulation occurs in the whole temperature range. Leakage current at 3 kV increases with temperature, while being three orders of magnitude lower than those of equivalent Si diodes. Double-pulse switching tests reveal the 10 kV SiC PiN diode’s outstanding performance. Turn-on dV/dt and di/dt are −32 V/ns and 311 A/µs, respectively, whereas turn-off dV/dt and di/dt are 474 V/ns and −4.2 A/ns.

Performance and hot-carrier reliability of 100 nm channel length jet vapor deposited Si/sub 3/N/sub 4/ MNSFETs

2001 ◽  
Vol 48 (4) ◽  
pp. 679-684 ◽  
Author(s):  
S. Mahapatra ◽  
V.R. Rao ◽  
B. Cheng ◽  
M. Khare ◽  
C.D. Parikh ◽  
...  
Keyword(s):  
Channel Length ◽  
Hot Carrier

Investigation of hot-carrier induced degradation in 0.1μm channel length n-MOSFET's

1993 ◽  
Vol 22 (1-4) ◽  
pp. 293-296 ◽  
Author(s):  
N. Revil ◽  
J.P. Miéville ◽  
S. Cristoloveanu ◽  
M. Dutoit ◽  
P. Mortini
Keyword(s):  
Channel Length ◽  
Hot Carrier
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