Subthreshold reference circuit with curvature compensation based on the channel length modulation of MOS devices

2021 ◽  
Author(s):  
Hamed Aminzadeh
Keyword(s):  
Channel Length ◽  
Mos Devices ◽  
Reference Circuit

scholarly journals A high supply voltage bandgap reference circuit using drain-extended MOS devices

2013 ◽  
Vol 10 (8) ◽  
pp. 20130142-20130142
Author(s):  
Geun Rae Cho ◽  
Kyung Woon Hwang ◽  
Tag Gon Kim
Keyword(s):  
Supply Voltage ◽  
Bandgap Reference ◽  
Mos Devices ◽  
Reference Circuit

scholarly journals New Method for Determination of Drain Saturation Voltage in Short Channel MOS Devices Between Liquid Helium to Room Temperature

2001 ◽  
Vol 24 (2) ◽  
pp. 129-134
Author(s):  
Y. Amhouche ◽  
A. El Abbassi ◽  
K. Raïs ◽  
E. Bendada ◽  
R. Rmaily
Keyword(s):  
Room Temperature ◽  
Impact Ionization ◽  
Ionization Rate ◽  
Channel Length ◽  
New Method ◽  
Short Channel ◽  
Mos Devices ◽  
Impact Ionization Rate ◽  
The Impact

A new method for drain saturation voltage extraction in submicron MOSFETs is presented. It is based on measurements of the partial derivative of the impact ionization rate. The method has been tested using main of channel length MOSFET devices and compared with others methods.

High Performance Polycrystalline Silicon Thin Film Devices

1985 ◽  
Vol 49 ◽  
Author(s):  
William G. Hawkins
Keyword(s):  
Thin Film ◽  
Polycrystalline Silicon ◽  
High Performance ◽  
Channel Length ◽  
Large Area ◽  
Silicon Thin Film ◽  
Leakage Currents ◽  
Silicon Devices ◽  
Mos Devices ◽  
Threshold Voltages

AbstractThe goal of this work was to produce a fabrication process for high performance polycrystalline silicon thin film MOS devices. We have fabricated p-channel devices with mobilities of 35 cm2/V-sec and n-channel devices with mobilities of 50 cm2/V-sec by tailoring the process for depositon of the channel layer, by gate oxidation of the channel at high temperature, and by use of plasma hydrogenation. Under optimal conditions deduced from the study, device threshold voltages are close to zero. Leakage currents in the off-state are less than 0.1 pA/µm of channel length. Fabrication of the devices requires four mask levels and employs standard process steps. Therefore, polycrystalline silicon devices are attractive candidates for a variety of electronics applications, including thin film logic over large area.

scholarly journals Wide-Supply-Voltage-Range CMOS Bandgap Reference for In Vivo Wireless Power Telemetry

Energies ◽  
2020 ◽  
Vol 13 (11) ◽  
pp. 2986 ◽  
Author(s):  
Ruhaifi Bin Abdullah Zawawi ◽  
Wajahat H. Abbasi ◽  
Seung-Hwan Kim ◽  
Hojong Choi ◽  
Jungsuk Kim
Keyword(s):  
Power Supply ◽  
Supply Voltage ◽  
Channel Length ◽  
Power Supply Voltage ◽  
Voltage Range ◽  
Power Supply Rejection Ratio ◽  
Wide Range ◽  
Reference Circuit ◽  
Inherent Problem

The robustness of the reference circuit in a wide range of supply voltages is crucial in implanted devices. Conventional reference circuits have demonstrated a weak performance over wide supply ranges. Channel-length modulation in the transistors causes the circuit to be sensitive to power supply variation. To solve this inherent problem, this paper proposes a new output-voltage-line-regulation controller circuit. When a variation occurs in the power supply, the controller promptly responds to the supply deviation and removes unwanted current in the output path of the reference circuit. The proposed circuit was implemented in a 0.35-μm SK Hynix CMOS standard process. The experimental results demonstrated that the proposed reference circuit could generate a reference voltage of 0.895 V under a power supply voltage of 3.3 V, line regulation of 1.85 mV/V in the supply range of 2.3 to 5 V, maximum power supply rejection ratio (PSRR) of −54 dB, and temperature coefficient of 11.9 ppm/°C in the temperature range of 25 to 100 °C.

Latchup Free Lateral Cmos on Laser Recrystallized Silicon

1985 ◽  
Vol 53 ◽  
Author(s):  
S. Sritharan ◽  
R. Solanki ◽  
G. J. Collins ◽  
J. Fukumoto ◽  
N. Szluk ◽  
...  
Keyword(s):  
Oxide Layer ◽  
Leakage Current ◽  
Silicon Layer ◽  
Channel Length ◽  
Ring Oscillators ◽  
Surface Electron ◽  
Mos Devices ◽  
Thick Oxide Layer ◽  
Subthreshold Leakage ◽  
Nmos Transistors

ABSTRACTLatchup free CMOS devices have been fabricated by forming PMOS transistors in a 0.5μm thick laser recrystallized silicon layer. This recrystallized layer is isolated fram the bulk wafer by a lμm thick oxide layer. The NMOS transistors were fabricated both in the bulk wafer in the region which was used as the recrystallization seeds, as well as in the recrystallized silicon layer itself. Ring oscillators fabricated with 3μm channel length using a bi-layer lateral CMOS structure show a naninal delay of 1.7ns/stage. The MOS devices fabricated in the recrystallized silicon show low subthreshold leakage current, and surface electron and hole mobilities of 580cm2/V.s and 210cm2/V.s respectively.

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