Modeling of Triangular Sacrificial Layer Residue Effect in Nano-Electro-Mechanical Nonvolatile Memory

In recent years, there has been a growing interest in the application of ferroelectric thin films for nonvolatile memory applications and as a gate insulator in DRAM structures. In addition, bulk ferroelectric materials are also widely used as components in electronic circuits and find numerous applications in sensors and actuators. To a large extent, the performance of ferroelectric materials are governed by the ferroelectric domains (with dimensions in the micron to sub-micron range) and the switching of domains in the presence of an applied field. Conventional TEM studies of ferroelectric domains structures, in conjunction with in-situ studies of the domain interactions can aid in explaining the behavior of ferroelectric materials, while providing some answers to the mechanisms and processes that influence the performance of ferroelectric materials. A few examples from bulk and thin film ferroelectric materials studied using the TEM are discussed below.Figure 1 shows micrographs of ferroelectric domains obtained from undoped and Fe-doped BaTiO3 single crystals. The domain boundaries have been identified as 90° domains with the boundaries parallel to <011>.

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Epitaxial ferroelectric thin films

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100170591 ◽

1994 ◽

Vol 52 ◽

pp. 572-573

Author(s):

S. G. Ghonge ◽

E. Goo ◽

R. Ramesh ◽

R. Haakenaasen ◽

D. K. Fork

Keyword(s):

Single Crystal ◽

Work Function ◽

Nonvolatile Memory ◽

Ferroelectric Properties ◽

Electrical Contact ◽

Memory Devices ◽

Ferroelectric Films ◽

Si Substrates ◽

Electro Optic ◽

Wide Range

Microstructure of epitaxial ferroelectric/conductive oxide heterostructures on LaAIO3(LAO) and Si substrates have been studied by conventional and high resolution transmission electron microscopy. The epitaxial films have a wide range of potential applications in areas such as non-volatile memory devices, electro-optic devices and pyroelectric detectors. For applications such as electro-optic devices the films must be single crystal and for applications such as nonvolatile memory devices and pyroelectric devices single crystal films will enhance the performance of the devices. The ferroelectric films studied are Pb(Zr0.2Ti0.8)O3(PLZT), PbTiO3(PT), BiTiO3(BT) and Pb0.9La0.1(Zr0.2Ti0.8)0.975O3(PLZT).Electrical contact to ferroelectric films is commonly made with metals such as Pt. Metals generally have a large difference in work function compared to the work function of the ferroelectric oxides. This results in a Schottky barrier at the interface and the interfacial space charge is believed to responsible for domain pinning and degradation in the ferroelectric properties resulting in phenomenon such as fatigue.

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High Quality HfO2 Film and Its Applications in Novel Poly-Si Devices

MRS Proceedings ◽

10.1557/proc-716-b2.6 ◽

2002 ◽

Vol 716 ◽

Author(s):

K.L. Ng ◽

N. Zhan ◽

M.C. Poon ◽

C.W. Kok ◽

M. Chan ◽

...

Keyword(s):

Barrier Height ◽

Nonvolatile Memory ◽

Dielectric Material ◽

Tunneling Current ◽

Interface Layer ◽

Si Substrate ◽

Hfo2 Film ◽

Effective Barrier Height ◽

Effective Barrier ◽

Nonvolatile Memory Devices

AbstractHfO2 as a dielectric material in MOS capacitor by direct sputtering of Hf in an O2 ambient onto a Si substrate was studied. The results showed that the interface layer formed between HfO2 and the Si substrate was affected by the RTA time in the 500°C annealing temperature. Since the interface layer is mainly composed of hafnium silicate, and has high interface trap density, the effective barrier height is therefore lowered with increased RTA time. The change in the effective barrier height will affect the FN tunneling current and the operation of the MOS devices when it is applied for nonvolatile memory devices.

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Carbon Coating for Electron Beam Testing and Focus Ion Beam Reconfiguration

ISTFA 1996: Conference Proceedings from the 22nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa1996p0333 ◽

1996 ◽

Author(s):

P. Perdu ◽

G. Perez ◽

M. Dupire ◽

B. Benteo

Keyword(s):

Electron Beam ◽

Sample Preparation ◽

Carbon Coating ◽

Focused Ion Beam ◽

Sacrificial Layer ◽

Ion Beam ◽

Electrical Characterization ◽

Fault Analysis ◽

Voltage Contrast ◽

The Right

Abstract To debug ASIC we likely use accurate tools such as an electron beam tester (Ebeam tester) and a Focused Ion Beam (FIB). Interactions between ions or electrons and the target device build charge up on its upper glassivation layer. This charge up could trigger several problems. With Ebeam testing, it sharply decreases voltage contrast during Image Fault Analysis and hide static voltage contrast. During ASIC reconfiguration with FIB, it could induce damages in the glassivation layer. Sample preparation is getting a key issue and we show how we can deal with it by optimizing carbon coating of the devices. Coating is done by an evaporator. For focused ion beam reconfiguration, we need a very thick coating. Otherwise the coating could be sputtered away due to imaging. This coating is use either to avoid charge-up on glassivated devices or as a sacrificial layer to avoid short circuits on unglassivated devices. For electron beam Testing, we need a very thin coating, we are now using an electrical characterization method with an insitu control system to obtain the right thin thickness. Carbon coating is a very cheap and useful method for sample preparation. It needs to be tuned according to the tool used.

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