scholarly journals Deep PUF: A Highly Reliable DRAM PUF-Based Authentication for IoT Networks Using Deep Convolutional Neural Networks

Sensors ◽  
2021 ◽  
Vol 21 (6) ◽  
pp. 2009
Author(s):  
Fatemeh Najafi ◽  
Masoud Kaveh ◽  
Diego Martín ◽  
Mohammad Reza Mosavi
Keyword(s):  
Error Correction ◽  
Random Access ◽  
Error Correction Codes ◽  
Access Memory ◽  
Deep Convolutional Neural Networks ◽  
Device Identification ◽  
Physical Unclonable Functions ◽  
Server Side ◽  
Correction Technique ◽  
Reduction Methods

Traditional authentication techniques, such as cryptographic solutions, are vulnerable to various attacks occurring on session keys and data. Physical unclonable functions (PUFs) such as dynamic random access memory (DRAM)-based PUFs are introduced as promising security blocks to enable cryptography and authentication services. However, PUFs are often sensitive to internal and external noises, which cause reliability issues. The requirement of additional robustness and reliability leads to the involvement of error-reduction methods such as error correction codes (ECCs) and pre-selection schemes that cause considerable extra overheads. In this paper, we propose deep PUF: a deep convolutional neural network (CNN)-based scheme using the latency-based DRAM PUFs without the need for any additional error correction technique. The proposed framework provides a higher number of challenge-response pairs (CRPs) by eliminating the pre-selection and filtering mechanisms. The entire complexity of device identification is moved to the server side that enables the authentication of resource-constrained nodes. The experimental results from a 1Gb DDR3 show that the responses under varying conditions can be classified with at least a 94.9% accuracy rate by using CNN. After applying the proposed authentication steps to the classification results, we show that the probability of identification error can be drastically reduced, which leads to a highly reliable authentication.

scholarly journals OBET: On-the-Fly Byte-Level Error Tracking for Correcting and Detecting Faults in Unreliable DRAM Systems

Sensors ◽  
2021 ◽  
Vol 21 (24) ◽  
pp. 8271
Author(s):  
Duy-Thanh Nguyen ◽  
Nhut-Minh Ho ◽  
Weng-Fai Wong ◽  
Ik-Joon Chang
Keyword(s):  
Operating System ◽  
Error Correction ◽  
High Performance ◽  
State Of The Art ◽  
Random Access ◽  
Random Access Memory ◽  
Error Correction Codes ◽  
System Failure ◽  
Access Memory ◽  
Technology Scaling

With technology scaling, maintaining the reliability of dynamic random-access memory (DRAM) has become more challenging. Therefore, on-die error correction codes have been introduced to accommodate reliability issues in DDR5. However, the current solution still suffers from high overhead when a large DRAM capacity is used to deliver high performance. We present a DRAM chip architecture that can track faults at byte-level DRAM cell errors to address this problem. DRAM faults are classified as temporary or permanent in our proposed architecture, with no additional pins and with minor DRAM chip modifications. Hence, we achieve reliability comparable to that of other state-of-the-art solutions while incurring negligible performance and energy overhead. Furthermore, the faulty locations are efficiently exposed to the operating system (OS). Thus, we can significantly reduce the required scrubbing cycle by scrubbing only faulty DRAM pages while reducing the system failure probability up to 5000∼7000 times relative to conventional operation.

scholarly journals Pitfall of the Strongest Cells in Static Random Access Memory Physical Unclonable Functions

Sensors ◽  
2018 ◽  
Vol 18 (6) ◽  
pp. 1776 ◽  
Author(s):  
Mingyang Gong ◽  
Hailong Liu ◽  
Run Min ◽  
Zhenglin Liu
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Access Memory ◽  
Physical Unclonable Functions

Multi-Valued Physical Unclonable Functions based on Dynamic Random Access Memory

2020 ◽  
Author(s):  
Sven Müelich ◽  
Chirag Sudarshan ◽  
Christian Weis ◽  
Martin Bossert ◽  
Robert F.H. Fischer ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Dynamic Random Access Memory ◽  
Access Memory ◽  
Physical Unclonable Functions

scholarly journals Intrinsic Physical Unclonable Function (PUF) Sensors in Commodity Devices

Sensors ◽  
2019 ◽  
Vol 19 (11) ◽  
pp. 2428 ◽  
Author(s):  
Shuai Chen ◽  
Bing Li ◽  
Yuan Cao
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Experimental Results ◽  
Raspberry Pi ◽  
Key Generation ◽  
Access Memory ◽  
Physical Unclonable Functions ◽  
Security Authentication ◽  
Commercial Off The Shelf ◽  
Intrinsic Dynamic

The environment-dependent feature of physical unclonable functions (PUFs) is capable of sensing environment changes. This paper presents an analysis and categorization of a variety of PUF sensors. Prior works have demonstrated that PUFs can be used as sensors while providing a security authentication assurance. However, most of the PUF sensors need a dedicated circuit. It can be difficult to implemented in commercial off-the-shelf devices. This paper focuses on the intrinsic Dynamic Random Access Memory (DRAM) PUF-based sensors, which requires no modifications for hardware. The preliminary experimental results on Raspberry Pi have demonstrated the feasibility of our design. Furthermore, we configured the DRAM PUF-based sensor in a DRAM PUF-based key generation scheme which improves the practicability of the design.

Analysis of FSRAM Single Bit Failures Due to Unique Dislocations

1998 ◽  
Author(s):  
Phil Schani ◽  
S. Subramanian ◽  
Vince Soorholtz ◽  
Pat Liston ◽  
Jamey Moss ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Temperature Sensitive ◽  
Wafer Level ◽  
Top Down ◽  
Access Memory ◽  
Transmission Electron ◽  
Contact Processing

Abstract Temperature sensitive single bit failures at wafer level testing on 0.4µm Fast Static Random Access Memory (FSRAM) devices are analyzed. Top down deprocessing and planar Transmission Electron Microscopy (TEM) analyses show a unique dislocation in the substrate to be the cause of these failures. The dislocation always occurs at the exact same location within the bitcell layout with respect to the single bit failing data state. The dislocation is believed to be associated with buried contact processing used in this type of bitcell layout.

Deprocessing Methodologies for Detection of IBC and Cell-to-Cell Shorts in Submicron DRAM

2012 ◽  
Author(s):  
Ramachandra Chitakudige ◽  
Sarat Kumar Dash ◽  
A.M. Khan
Keyword(s):  
High Selectivity ◽  
Electron Cyclotron Resonance ◽  
Random Access ◽  
Random Access Memory ◽  
Access Memory ◽  
Plasma System ◽  
Poly Silicon ◽  
Hazardous Gases ◽  
Wet Etch ◽  
Resonance Plasma

Abstract Detection of both Insufficient Buried Contact (IBC) and cell-to-cell short defects is quite a challenging task for failure analysis in submicron Dynamic Random Access Memory (DRAM) devices. A combination of a well-controlled wet etch and high selectivity poly silicon etch is a key requirement in the deprocessing of DRAM for detection of these types of failures. High selectivity poly silicon etch methods have been reported using complicated system such as ECR (Electron Cyclotron Resonance) Plasma system. The fact that these systems use hazardous gases like Cl2, HBr, and SF6 motivates the search for safer alternative deprocessing chemistries. The present work describes high selectivity poly silicon etch using simple Reactive Ion Etch (RIE) plasma system using less hazardous gases such as CF4, O2 etc. A combination of controlled wet etch and high selectivity poly silicon etch have been used to detect both IBC and cell-to-cell shorts in submicron DRAMs.

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