INFLUENCE OF RAPID THERMAL TREATMENT OF INITIAL SILICON WAFERS ON THE ELECTROPHYSICAL PROPERTIES OF SILICON DIOXIDE OBTAINED BY PYROGENOUS OXIDATION

The key element determining stability of the semiconductor devices is a gate dielectric. As its thickness reduces in the process of scaling the combined volume of factors determining its electrophysical properties increases. The purpose of this paper is development of the control express method of the error-free running time of the gate dielectric and study the influence of the rapid thermal treatment of the initial silicon wafers and gate dielectric on its reliability.The paper proposes a model for evaluation of the reliability indicators of the gate dielectrics as per the trial results of the test MDS-structures by means of applying of the ramp-increasing voltage on the gate up to the moment of the structure breakdown at various velocities of the voltage sweep with measurement of the IV-parameters. The proposed model makes it possible to realize the express method of the reliability evaluation of the thin dielectrics right in the production process of the integrated circuits.On the basis of this method study of the influence of the rapid thermal treatment of the initial silicon wafers of the KEF 4.5, KDB 12 wafers and formed on them by means of the pyrogenic oxidation of the gate dielectric for the error-free running time were performed. It is shown, that rapid thermal treatment of the initial silicon wafers with their subsequent oxidation results in increase of the error-free running time of the gate dielectric on average from 12.9 to 15.9 years (1.23 times greater). Thermal treatment of the initial silicon wafers and gate dielectric makes it possible to expand the error-free running time up to 25.2 years, i.e.1.89 times more, than in the standard process of the pyrogenic oxidation and 1.5 times more, than under application of the rapid thermal treatment of the initial silicon wafers only.

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Influence of Fast Thermal Treatment on the Electrophysical Properties of Silicon Dioxide

Journal of Engineering Physics and Thermophysics ◽

10.1007/s10891-018-1866-0 ◽

2018 ◽

Vol 91 (5) ◽

pp. 1337-1341

Author(s):

V. A. Pilipenko ◽

V. A. Solodukha ◽

V. A. Gorushko

Keyword(s):

Thermal Treatment ◽

Silicon Dioxide ◽

Electrophysical Properties

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73. Thickness measurement by ultraviolet visible interference method of silicon dioxide layers deposited on polished silicon wafers

Vacuum ◽

10.1016/0042-207x(65)92356-0 ◽

1965 ◽

Vol 15 (1) ◽

pp. 46

Keyword(s):

Silicon Dioxide ◽

Thickness Measurement ◽

Silicon Wafers ◽

Interference Method

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Pts-Oi Complex Formation in Platinum Diffused Silicon

MRS Proceedings ◽

10.1557/proc-864-e2.3 ◽

2005 ◽

Vol 864 ◽

Author(s):

Wilfried Vervisch ◽

Laurent Ventura ◽

Bernard Pichaud ◽

Gérard Ducreux ◽

André Lhorte

Keyword(s):

Thermal Treatment ◽

Complex Formation ◽

Cooling Rate ◽

Point Defects ◽

Diffusion Processes ◽

Silicon Wafers ◽

Doping Behaviour ◽

Simulation Results ◽

Dopant Atoms ◽

P Type

AbstractWhen platinum is diffused at temperatures higher than 900°C in Cz or FZ low doped n-type silicon samples, which are then cooled slowly in the range [1-10]°C/min, a p-type doping leading to the formation of a pn junction can be observed by spreading resistance measurement. The lower the cooling rate, the deeper the junction is. This junction disappears after a second thermal treatment finishing with a quenching step. A platinum related complex formation is considered to explain this reversible doping behaviour. Different possible interactions between platinum and other impurities such as dopant atoms, intrinsic point defects, and common residual impurities (C, Oi, transition metallic atoms) are studied here. Experimental results from Pt diffusion processes in different qualities of silicon wafers, and simulation results, lead to the conclusion that the platinum related p-type doping effect is due to the formation of a Pts-Oi complex.

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KOH-ETCH Related Defects on Processed Silicon Wafers

MRS Proceedings ◽

10.1557/proc-259-187 ◽

1992 ◽

Vol 259 ◽

Cited By ~ 1

Author(s):

Laurent E. Kassel

Keyword(s):

Thermal Treatment ◽

Epitaxial Growth ◽

Silicon Wafers ◽

Processing Steps ◽

Crystallographic Orientations

ABSTRACTKOH, an anisotropic etchant of monocrystalline Si, may cause roughness and defects whose shapes are related to crystallographic orientations. This paper studies the effect of processing steps on the formation of geometric etch defects. Implantation, thermal treatment, epitaxial growth or photoresist were not the source of such defects. In the scope of this study, only unwanted damage caused geometric etch defects. This makes the observation of the wafer after KOH etch a good indicator of the quality of previous steps.

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