scholarly journals Design and Analysis of High Gain, Low Power and Low Voltage a-Si TFT based Operational Amplifier

2015 ◽  
Vol 8 (16) ◽  
Author(s):  
G. Prabhakaran ◽  
V. Kannan
Electronics ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 74
Author(s):  
Na Bai ◽  
Xiaolong Li ◽  
Yaohua Xu

Based on the SMIC 0.13 um CMOS technology, this paper uses a 0.8 V supply voltage to design a low-voltage, ultra-low-power, high-gain, two-stage, fully differential operational amplifier. Through the simulation analysis, when the supply voltage is 0.8 V, the design circuit meets the ultra-low power consumption and also has the characteristic of high gain. The five-tube, fully differential, and common-source amplifier circuits provide the operational amplifier with high gain and large swing. Unlike the traditional common-mode feedback, this paper uses the output of the common-mode feedback as the bias voltage of the five-tube operational transconductance amplifier load, which reduces the design cost of the circuit; the structure involves self-cascoding composite MOS, which makes the common-mode feedback loop more sensitive. The frequency compensation circuit adopts Miller compensation technology with zero-pole separation, which increases the stability of the circuit. The input of the circuit uses the current mirror. A small reference current is chosen to reduce power consumption. A detailed performance simulation analysis of this operational amplifier circuit is carried out on the Cadence spectre platform. The open-loop gain of this operational amplifier is 74.1 dB, the phase margin is 61°, the output swing is 0.7 V, the common-mode rejection ratio is 109 dB, and the static power consumption is only 11.2 uW.


2014 ◽  
Vol 23 (08) ◽  
pp. 1450108 ◽  
Author(s):  
VANDANA NIRANJAN ◽  
ASHWANI KUMAR ◽  
SHAIL BALA JAIN

In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.


Author(s):  
A. Jeevan Kumar ◽  
K. Lokesh Krishna ◽  
K. Abhinav Viswateja ◽  
K. Gopi ◽  
S. Mohan Rao ◽  
...  

Author(s):  
No Myoung ◽  
Ho Kang ◽  
Seok Kim ◽  
Byoung Choi ◽  
Seong-su Park ◽  
...  
Keyword(s):  

Author(s):  
Hassan Faraji Baghtash ◽  
Rasoul Pakdel

low-voltage, low-power, rail-to-rail, two-stage trans-conductance amplifier is presented. The structure exploits body-driven transistors, configured in folded-cascode structure. To reduce the power consumption, the transistors are biased in the subthreshold region. The Specter RF simulation results which are conducted in TSMC 180nm CMOS standard process proves the well-performance of the proposed structure. The performance of the proposed structure against process variations is checked through process corners and Monte Carlo simulations. The results prove the robustness of the proposed amplifier against process uncertainties. Some important specifications of the design derived from circuit simulations are 93.36 dB small-signal gain, 14.4 PV2/Hz input referred noise power, 26.5 kHz unity gain frequency, 20 V/ms slew rate. The proposed structure draws 260 nW power from 0.5 V power supply and is loaded with a 15 pF loading capacitor. The input common mode range of structure is from 0 to 0.5 V.


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