scholarly journals Comparative Analysis Study on SSD, HDD, and SSHD

2021 ◽  
Vol 12 (3) ◽  
pp. 3635-3641
Author(s):  
Ms.Hepisuthar Et.al
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Time Data ◽  
Data Movement ◽  
Storage Devices ◽  
User Input ◽  
Current Century ◽  
Long Time ◽  
Computing Speed

In the Current Century, permeant storage devices and methods of storing data changed from traditional HDD to SDD. In this document, we discuss the merge of HDD and SSD. The Abbreviation of SSHD is called the solid-state hybrid disk. A mixture of both secondary devices to enhance the performance of the system. Inside the SSD, data movement events occur without any user input. Recent research has suggested that SSD has only the Replacement of secondary storage. HDD is also good in life span with longer life. It’s more reliable for long time data contained in this. HDD storage has typical magnetic fields for store data. SSD contains NAND flash memory to write the data in the drive. Based on the method and material of storing different. HDD and SSD feature well to upgrade with technology in Computer filed. For enhancing computing speed and excellent processing SSHD good to use in computer.Ratio increase of SSHD usage in current laptop and in computer system.

scholarly journals Compression-Assisted Adaptive ECC and RAID Scattering for NAND Flash Storage Devices

Sensors ◽  
2020 ◽  
Vol 20 (10) ◽  
pp. 2952 ◽  
Author(s):  
Seung-Ho Lim ◽  
Ki-Woong Park
Keyword(s):  
Flash Memory ◽  
Error Recovery ◽  
Recovery Phase ◽  
Error Correction Codes ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Flash Storage ◽  
Storage Devices ◽  
Complementary Method ◽  
Compressed Data

NAND flash memory-based storage devices are vulnerable to errors induced by NAND flash memory cells. Error-correction codes (ECCs) are integrated into the flash memory controller to correct errors in flash memory. However, since ECCs show inherent limits in checking the excessive increase in errors, a complementary method should be considered for the reliability of flash storage devices. In this paper, we propose a scheme based on lossless data compression that enhances the error recovery ability of flash storage devices, which applies to improve recovery capability both of inside and outside the page. Within a page, ECC encoding is realized on compressed data by the adaptive ECC module, which results in a reduced code rate. From the perspective of outside the page, the compressed data are not placed at the beginning of the page, but rather is placed at a specific location within the page, which makes it possible to skip certain pages during the recovery phase. As a result, the proposed scheme improves the uncorrectable bit error rate (UBER) of the legacy system.

NAND Flash Memory With Multiple Page Sizes for High-Performance Storage Devices

2016 ◽  
Vol 24 (2) ◽  
pp. 764-768 ◽  
Author(s):  
Jin-Young Kim ◽  
Sang-Hoon Park ◽  
Hyeokjun Seo ◽  
Ki-Whan Song ◽  
Sungroh Yoon ◽  
...  
Keyword(s):  
Flash Memory ◽  
High Performance ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Storage Devices

scholarly journals A Stepwise Rate-Compatible LDPC and Parity Management in NAND Flash Memory-Based Storage Devices

IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 162491-162506
Author(s):  
Seung-Ho Lim ◽  
Jae-Bin Lee ◽  
Geon-Myeong Kim ◽  
Woo Hyun Ahn
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Storage Devices

Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)

2012 ◽  
Vol E95.C (5) ◽  
pp. 837-841 ◽  
Author(s):  
Se Hwan PARK ◽  
Yoon KIM ◽  
Wandong KIM ◽  
Joo Yun SEO ◽  
Hyungjin KIM ◽  
...  
Keyword(s):  
Flash Memory ◽  
Three Dimensional ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Memory Array

scholarly journals Artificial Neural Network Assisted Error Correction for MLC NAND Flash Memory

Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 879
Author(s):  
Ruiquan He ◽  
Haihua Hu ◽  
Chunru Xiong ◽  
Guojun Han
Keyword(s):  
Neural Network ◽  
Error Correction ◽  
Error Detection ◽  
Flash Memory ◽  
Nand Flash ◽  
Data Reliability ◽  
Nand Flash Memory ◽  
Process Technology ◽  
Noise Mitigation ◽  
Memory Channel

The multilevel per cell technology and continued scaling down process technology significantly improves the storage density of NAND flash memory but also brings about a challenge in that data reliability degrades due to the serious noise. To ensure the data reliability, many noise mitigation technologies have been proposed. However, they only mitigate one of the noises of the NAND flash memory channel. In this paper, we consider all the main noises and present a novel neural network-assisted error correction (ANNAEC) scheme to increase the reliability of multi-level cell (MLC) NAND flash memory. To avoid using retention time as an input parameter of the neural network, we propose a relative log-likelihood ratio (LLR) to estimate the actual LLR. Then, we transform the bit detection into a clustering problem and propose to employ a neural network to learn the error characteristics of the NAND flash memory channel. Therefore, the trained neural network has optimized performances of bit error detection. Simulation results show that our proposed scheme can significantly improve the performance of the bit error detection and increase the endurance of NAND flash memory.

scholarly journals Investigation of Re-program Scheme in Charge Trap Based 3D NAND Flash Memory

2021 ◽  
pp. 1-1
Author(s):  
Ting Cheng ◽  
Jianquan Jia ◽  
Lei Jin ◽  
Xinlei Jia ◽  
Shiyu Xia ◽  
...  
Keyword(s):  
Flash Memory ◽  
Program Scheme ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Charge Trap
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