Evaluation of an OpenCL-Based FPGA Platform for Particle Filter

2016 ◽  
Vol 20 (5) ◽  
pp. 743-754 ◽  
Author(s):  
Shunsuke Tatsumi ◽  
◽  
Masanori Hariyama ◽  
Norikazu Ikoma ◽  
Keyword(s):  
Particle Filter ◽  
Fpga Implementation ◽  
Design Tool ◽  
Computational Time ◽  
Major Drawback ◽  
Large Power ◽  
Internal States ◽  
Field Programmable ◽  
Power Delay Product ◽  
High Level

Particle filter is one promising method to estimate the internal states in dynamical systems, and can be used for various applications such as visual tracking and mobile-robot localization. The major drawback of particle filter is its large computational amount, which causes long computational-time and large power-consumption. In order to solve this problem, this paper proposes an Field-Programmable Gate Array (FPGA) platform for particle filter. The platform is designed using the OpenCL-based design tool that allows users to develop using a high-level programming language based on C and to change designs easily for various applications. The implementation results demonstrate the proposed FPGA implementation is 106 times faster than the CPU one, and the power-delay product of the FPGA implementation is 1.1% of the CPU one. Moreover, implementations for three different systems are shown to demonstrate flexibility of the proposed platform.

Fast FPGA Implementation for Computing the Pixel Purity Index of Hyperspectral Images

2017 ◽  
Vol 27 (03) ◽  
pp. 1850045 ◽  
Author(s):  
Jie Guo ◽  
Yunsong Li ◽  
Kai Liu ◽  
Jie Lei ◽  
Keyan Wang
Keyword(s):  
Hyperspectral Image ◽  
Fpga Implementation ◽  
Endmember Extraction ◽  
Overall Design ◽  
Real Time Analysis ◽  
Sensing Applications ◽  
Field Programmable ◽  
On Chip ◽  
High Level ◽  
Fast Field

The pixel purity index (PPI) algorithm is one of the most popular endmember extraction algorithms employed in hyperspectral image unmixing, which is too time-consuming to obtain real-time analysis in remote sensing applications. The fast field programmable gate array (FPGA) implementation for computing the PPI is proposed in this reported work. The parallel strategy by skewers consumes lower I/O bandwidth and on-chip memory capacity, and the Xilinx Vivado high-level-synthesis (HLS) tool speeds up our architecture design and implementation. The overall design can be simple to implement, and makes the FPGA hardware appealing for on-board hyperspectral unmixing.

scholarly journals FPGA IMPLEMENTATION OF CNN FOR DEFECT CLASSIFICATION ON CMP RING

2021 ◽  
Vol 83 (5) ◽  
pp. 101-108
Author(s):  
Ng Wai Kin ◽  
Mohd Shahrimie Mohd Asaari ◽  
Bakhtiar Affendi Rosdi ◽  
Muhammad Firdaus Akbar
Keyword(s):  
Chemical Mechanical Planarization ◽  
Fpga Implementation ◽  
Defect Inspection ◽  
Inference Process ◽  
Industrial Manufacturing ◽  
Human Labour ◽  
Field Programmable ◽  
Human Effort ◽  
High Level ◽  
Crucial Part

Defect inspection is a crucial part of industrial manufacturing. However, it relies heavily on human effort on manual visual inspection. Various machine vision techniques have been introduced to replace human labour and to improve inspection quality and efficiency. The limitation of these techniques is that the algorithms need to be engineered again with each different use case. In this work, a Convolutional Neural Network (CNN) is used to classify the defects of the Chemical Mechanical Planarization (CMP) ring. The trained CNN model achieved an accuracy of 91% and the time taken for each inference process is around 1800 msec. To achieve computational efficiency, the CNN model is performed on the embedded device. The previous implementation of embedded CNN deploys OpenCL-based high-level synthesis accelerator on a high-end Field Programmable Gate Array (FPGA) board. In this work, the model inference is accelerated by PipeCNN FPGA implementation on Cyclone-VSE DE1-SoC, a low-end embedded FPGA board. Several configurations of hardware parameters are tested to search for the best setup of the FPGA resources. The hardware implementation has improved approximately seven times faster, as the inference time for each classification has improved from 1800 msec to 250 msec. However, the model implemented using the hardware is observed to produce lower inference accuracy as the accuracy drops from 91% to 81%.

scholarly journals Smart sensing metasurface with self-defined functions in dual polarizations

Nanophotonics ◽  
2020 ◽  
Vol 9 (10) ◽  
pp. 3271-3278 ◽  
Author(s):  
Qian Ma ◽  
Qiao Ru Hong ◽  
Xin Xin Gao ◽  
Hong Bo Jing ◽  
Che Liu ◽  
...  
Keyword(s):  
Field Programmable Gate Array ◽  
The Other ◽  
Rf Power ◽  
Pin Diodes ◽  
Self Recognition ◽  
Field Programmable ◽  
Power Detector ◽  
Smart Sensing ◽  
High Level ◽  
Rf Power Detector

AbstractFor the intelligence of metamaterials, the -sensing mechanism and programmable reaction units are two important components for self-recognition and -determination. However, their realization still face great challenges. Here, we propose a smart sensing metasurface to achieve self-defined functions in the framework of digital coding metamaterials. A sensing unit that can simultaneously process the sensing channel and realize phase-programmable capability is designed by integrating radio frequency (RF) power detector and PIN diodes. Four sensing units distributed on the metasurface aperture can detect the microwave incidences in the x- and y-polarizations, while the other elements can modulate the reflected phase patterns under the control of a field programmable gate array (FPGA). To validate the performance, three schemes containing six coding patterns are presented and simulated, after which two of them are measured, showing good agreements with designs. We envision that this work may motivate studies on smart metamaterials with high-level recognition and manipulation.

scholarly journals A Modified KNN Algorithm for High-Performance Computing on FPGA of Real-Time m-QAM Demodulators

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 627
Author(s):  
David Marquez-Viloria ◽  
Luis Castano-Londono ◽  
Neil Guerrero-Gonzalez
Keyword(s):  
Real Time ◽  
High Performance ◽  
Interference Mitigation ◽  
Parallel Implementation ◽  
Computational Time ◽  
Successful Implementation ◽  
Interchannel Interference ◽  
The Difference ◽  
High Level ◽  
Performance Computing

A methodology for scalable and concurrent real-time implementation of highly recurrent algorithms is presented and experimentally validated using the AWS-FPGA. This paper presents a parallel implementation of a KNN algorithm focused on the m-QAM demodulators using high-level synthesis for fast prototyping, parameterization, and scalability of the design. The proposed design shows the successful implementation of the KNN algorithm for interchannel interference mitigation in a 3 × 16 Gbaud 16-QAM Nyquist WDM system. Additionally, we present a modified version of the KNN algorithm in which comparisons among data symbols are reduced by identifying the closest neighbor using the rule of the 8-connected clusters used for image processing. Real-time implementation of the modified KNN on a Xilinx Virtex UltraScale+ VU9P AWS-FPGA board was compared with the results obtained in previous work using the same data from the same experimental setup but offline DSP using Matlab. The results show that the difference is negligible below FEC limit. Additionally, the modified KNN shows a reduction of operations from 43 percent to 75 percent, depending on the symbol’s position in the constellation, achieving a reduction 47.25% reduction in total computational time for 100 K input symbols processed on 20 parallel cores compared to the KNN algorithm.

High Speed FPGA Based 128-bit Advance Encryption Standard (AES)

2021 ◽  
Vol 11 ◽  
Author(s):  
Ibrahem M. T. Hamidi ◽  
Farah S. H. Al-aassi
Keyword(s):  
High Throughput ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Design Tool ◽  
Advanced Encryption Standard ◽  
Clock Frequency ◽  
Advance Encryption Standard ◽  
Field Programmable ◽  
Internal Component ◽  
Gate Array

Aim: Achieve high throughput 128 bits FPGA based Advanced Encryption Standard. Background: Field Programmable Gate Array (FPGA) provides an efficient platform for design AES cryptography system. It provides the capability to control over each bit using HDL programming language such as VHDL and Verilog which results an output speed in Gbps rang. Objective: Use Field Programmable Gate Array (FPGA) to design high throughput 128 bits FPGA based Advanced Encryption Standard. Method: Pipelining technique has used to achieve maximum possible speed. The level of pipelining includes round pipelining and internal component pipelining where number of registers inserted in particular places to increase the output speed. The proposed design uses combinatorial logic to implement the byte substitution. The s-box implemented using composed field arithmetic with 7 stages of pipelining to reduce the combinatorial logic level. The presented model has implemented using VHDL in Xilinix ISETM 14.4 design tool. Result: The achieved results were 18.55 Gbps at a clock frequency of 144.96 MHz and area of 1568 Slices in Spartan3 xc3s1000 hardware. Conclusion: The results show that the proposed design reaches a high throughput with acceptable area usage compare with other designs in the literature.

scholarly journals Particle Filter with Gaussian Weighting for Vehicle Tracking

2011 ◽  
Vol 15 (6) ◽  
pp. 681-686
Author(s):  
Indah Agustien Siradjuddin ◽  
◽  
Muhammad Rahmat Widyanto ◽  
Keyword(s):  
Particle Filter ◽  
Object Tracking ◽  
Gaussian Distribution ◽  
Likelihood Function ◽  
Target Object ◽  
Video Data ◽  
Vehicle Tracking ◽  
Computational Time ◽  
Filter Method ◽  
Vehicle Motion

To track vehicle motion in data video, particle filter with Gaussian weighting is proposed. This method consists of four main stages. First, particles are generated to predict target’s location. Second, certain particles are searched and these particles are used to build Gaussian distribution. Third, weight of all particles is calculated based on Gaussian distribution. Fourth, particles are updated based on each weight. The proposed method could reduce computational time of tracking compared to that of conventional method of particle filter, since the proposed method does not have to calculate all particles weight using likelihood function. This method has been tested on video data with car as a target object. In average, this proposed method of particle filter is 60.61% times faster than particle filter method meanwhile the accuracy of tracking with this newmethod is comparable with particle filter method, which reach up to 86.87%. Hence this method is promising for real time object tracking application.

A Novel Power-Monitoring Strategy for Localization in Wireless Sensor Networks Using Antithetic Sampling Method

2020 ◽  
pp. 52-76
Author(s):  
Vasim Babu M.
Keyword(s):  
Monte Carlo ◽  
Sensor Node ◽  
Mapping Method ◽  
Computational Time ◽  
Localization Algorithm ◽  
Power Monitoring ◽  
Prime Objective ◽  
High Level ◽  
Power Mapping ◽  
Antithetic Sampling

The prime objective of this chapter is to develop a power-mapping localization algorithm based on Monte Carlo method using a discrete antithetic approach called Antithetic Markov Chain Monte Carlo (AMCMC). The chapter is focused on solving two major problems in WSN, thereby increasing the accuracy of the localization algorithm and discrete power control. Consecutively, the work is focused to reduce the computational time, while finding the location of the sensor. The model achieves the power controlling strategy using discrete power levels (CC2420 radio chip) which allocate the power, based on the event of each sensor node. By utilizing this discrete power mapping method, all the high-level parameters are considered for WSN. To improve the overall accuracy, the antithetic sampling is used to reduce the number of unwanted sampling, while identifying the sensor location in each transition state. At the final point, the accuracy is increased to 94% wherein nearly 24% of accuracy is increased compared to other MCL-based localization schemes.

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