scholarly journals Power optimisation using intelligent Clock gating dedicated for block RAM cascading technique in FPGA design.

2021 ◽  
Author(s):  
gurwinder singh ◽  
Munish Rattan ◽  
Gurjot Kaur Walia
Keyword(s):  
Digital Circuits ◽  
Current Trend ◽  
Critical Energy ◽  
Clock Gating ◽  
Fpga Design ◽  
Gate Arrays ◽  
Field Programmable ◽  
Chip Size ◽  
Programmable Gate Arrays ◽  
High Level

Abstract The current trend is the combination of chip size reduction and an increase in the number of circuits on chips has provided significant growth in battery consumption and critical energy efficiency leading to growth in the emerging Low Power Electronics sector. Our paper is committed to optimizing the power by eliminating cascading in block RAM. It dominates the amount of power dissipated in SOCs (System on Chips). High-level integration (HLS) allows hardware designers to think logically and not worry about low-level, cyclical details. It arranges the capability to quickly access the slot of design and the tradeoff between resource utilization and operation. Field Programmable Gate Arrays (FP- GAs) show significant progress in measuring speed and capacity to create a platform for the use of digital circuits. In the design of the FPGA, integration tools are used that perform various mitigation and improvement strategies. Integration tools utilize the RTL representation of a project with time constraints and generate a network list of the same level. Today, the advanced Xilinx Vivado Design Suite is used for FPGA design as a blending tool. In some cases, the Xilinx Vivado is unable to meet the required designer delays and power constraints. Therefore the primary goal of this paper is to optimize the power in design constraints in the Xilinx Vivado software.

scholarly journals On the Use of Magnetic RAMs in Field-Programmable Gate Arrays

2008 ◽  
Vol 2008 ◽  
pp. 1-9 ◽  
Author(s):  
Y. Guillemenet ◽  
L. Torres ◽  
G. Sassatelli ◽  
N. Bruchon
Keyword(s):  
Power Consumption ◽  
Random Access ◽  
Switching Scheme ◽  
Fpga Design ◽  
Gate Arrays ◽  
Magnetic Switching ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Time Required ◽  
Magnetic Tunneling

This paper describes the integration of field-induced magnetic switching (FIMS) and thermally assisted switching (TAS) magnetic random access memories in FPGA design. The nonvolatility of the latter is achieved through the use of magnetic tunneling junctions (MTJs) in the MRAM cell. A thermally assisted switching scheme helps to reduce power consumption during write operation in comparison to the writing scheme in the FIMS-MTJ device. Moreover, the nonvolatility of such a design based on either an FIMS or a TAS writing scheme should reduce both power consumption and configuration time required at each power up of the circuit in comparison to classical SRAM-based FPGAs. A real-time reconfigurable (RTR) micro-FPGA using FIMS-MRAM or TAS-MRAM allows dynamic reconfiguration mechanisms, while featuring simple design architecture.

Challenges in FPGA Technology Paradigm for the Implementation of IoT Applications

2020 ◽  
pp. 1-21
Author(s):  
Arul Murugan C. ◽  
Banuselvasaraswathy B.
Keyword(s):  
Internet Of Things ◽  
Field Programmable Gate Arrays ◽  
Modern World ◽  
Human Beings ◽  
Clock Gating ◽  
Gate Arrays ◽  
Iot Applications ◽  
Field Programmable ◽  
User Data ◽  
Programmable Gate Arrays

Internet of things (IoT) is a recent technology, and it will become the next generation of internet that connects several physical objects to interact amongst themselves without the assistance of human beings. It plays a significant role in our day-to-day lives and is used in several applications. IoT is a boon to this modern world, but it lacks in security. It cannot protect the user data from assailants, hackers, and vulnerabilities. Field programmable gate arrays (FPGA) helps to achieve all these objectives by incorporating secured end-to-end layer into its architecture. In this chapter, ultralow power and reduced area AES architecture with energy efficient DSE-S box techniques and clock gating for IoT applications are introduced. The proposed AES architecture is implemented over different FPGA families such as Cyclone I, Cyclone II, Virtex 5, and Kintex 7, respectively. From the experimental results, it is observed that the Kintex 7 FPGA kit consumes less power than other FPGA families.

Approaches for FPGA Design Assurance

2022 ◽  
Vol 15 (3) ◽  
pp. 1-29
Author(s):  
Eli Cahill ◽  
Brad Hutchings ◽  
Jeffrey Goeders
Keyword(s):  
Computer Aided Design ◽  
Fpga Design ◽  
Gate Arrays ◽  
Hardware Implementations ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Custom Hardware ◽  
Aided Design ◽  
Closed Source ◽  
Complex Computer

Field-Programmable Gate Arrays (FPGAs) are widely used for custom hardware implementations, including in many security-sensitive industries, such as defense, communications, transportation, medical, and more. Compiling source hardware descriptions to FPGA bitstreams requires the use of complex computer-aided design (CAD) tools. These tools are typically proprietary and closed-source, and it is not possible to easily determine that the produced bitstream is equivalent to the source design. In this work, we present various FPGA design flows that leverage pre-synthesizing or pre-implementing parts of the design, combined with open-source synthesis tools, bitstream-to-netlist tools, and commercial equivalence-checking tools, to verify that a produced hardware design is equivalent to the designer’s source design. We evaluate these different design flows on several benchmark circuits and demonstrate that they are effective at detecting malicious modifications made to the design during compilation. We compare our proposed design flows with baseline commercial design flows and measure the overheads to area and runtime.

AN EVOLUTIONARY ALGORITHM FOR THE ALLOCATION PROBLEM IN HIGH-LEVEL SYNTHESIS

2005 ◽  
Vol 14 (02) ◽  
pp. 347-366 ◽  
Author(s):  
HAIDAR M. HARMANANI ◽  
RONY SALIBA
Keyword(s):  
Evolutionary Algorithm ◽  
Allocation Problem ◽  
High Level Synthesis ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Functional Units ◽  
High Level ◽  
The Cost ◽  
Short Time

This paper presents an evolutionary algorithm to solve the datapath allocation problem in high-level synthesis. The method performs allocation of functional units, registers, and multiplexers in addition to controller synthesis with the objective of minimizing the cost of hardware resources. The system handles multicycle functional units as well as structural pipelining. The proposed method was implemented using C++ on a Linux workstation. We tested our method on a set of high-level synthesis benchmarks, all yielding good solutions in a short time. An integration path to Field Programmable Gate Arrays (FPGAs) is provided through VHDL.

scholarly journals Area Optimisation for Field-Programmable Gate Arrays in SystemC Hardware Compilation

2008 ◽  
Vol 2008 ◽  
pp. 1-14
Author(s):  
Johan Ditmar ◽  
Steve McKeever ◽  
Alex Wilson
Keyword(s):  
Clock Cycle ◽  
Gate Arrays ◽  
Field Programmable ◽  
Separate Block ◽  
Programmable Gate Arrays ◽  
Source Level ◽  
High Level ◽  
Specific Implementation ◽  
Mapping Arrays ◽  
Language Construct

This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area when targeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thus allowing a designer to concentrate more on an algorithm description and less on hardware-specific implementation details. The first algorithm is a source-level transformation implementing function exlining—where a separate block of hardware implements a function and is shared between multiple calls to the function. The second is a novel algorithm for mapping arrays to memories which involves assigning array accesses to memory ports such that no port is ever accessed more than once in a clock cycle. This algorithm assigns accesses to read/write only ports and read-write ports concurrently, solving the assignment problem more efficiently for a wider range of memories compared to existing methods. Both optimisations operate on a high-level program representation and have been implemented in a commercial SystemC compiler. Experiments show that in suitable circumstances these techniques result in significant reductions in logic utilisation for FPGAs.

A Gracefully Degrading and Energy-Efficient FPGA Programming using LabVIEW

2016 ◽  
Vol 5 (3) ◽  
pp. 165
Author(s):  
B. Naresh Kumar Reddy ◽  
N. Suresh ◽  
J.V.N. Ramesh
Keyword(s):  
Complex Signal ◽  
Graphical Language ◽  
Gate Arrays ◽  
Signal Flow Graphs ◽  
Field Programmable ◽  
Signal Processing Algorithms ◽  
Programmable Gate Arrays ◽  
Labview Fpga ◽  
High Level ◽  
Flow Graphs

<p>Programming of Field Programmable Gate Arrays (FPGAs) have long been the domain of engineers with VHDL or Verilog expertise. FPGA’s have caught the attention of algorithm developers and communication researchers, who want to use FPGAs to instantiate systems or implement DSP algorithms. These efforts however, are often stifled by the complexities of programming FPGAs. RTL programming in either VHDL or Verilog is generally not a high level of abstraction needed to represent the world of signal flow graphs and complex signal processing algorithms. This paper describes the FPGA Programs using Graphical Language rather than Verilog, VHDL with the help of LabVIEW and features of the LabVIEW FPGA environment.</p>

Combining Multiple Optimized FPGA-based Pulsar Search Modules Using OpenCL

2019 ◽  
Vol 08 (03) ◽  
pp. 1950008 ◽  
Author(s):  
Haomiao Wang ◽  
Prabu Thiagaraj ◽  
Oliver Sinnen
Keyword(s):  
High Speed ◽  
Design Space ◽  
Hardware Accelerators ◽  
Gate Arrays ◽  
Fast Prototyping ◽  
Multiple Input ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Square Kilometer Array ◽  
High Level

Field-Programmable Gate Arrays (FPGAs) are widely used in the central signal processing design of the Square Kilometer Array (SKA) as hardware accelerators. The frequency domain acceleration search (FDAS) module is an important part of the SKA1-MID pulsar search engine. To develop for a yet to be finalized hardware, for cross-discipline interoperability and to achieve fast prototyping, OpenCL as a high-level FPGA synthesis approaches employed to create the sub-modules of FDAS. The FT convolution and the harmonic-summing plus some other minor sub-modules are elements in the FDAS module that have been well-optimized separately before. In this paper, we explore the design space of combining well-optimized designs, dealing with the ensuing need to trade-off and compromise. Pipeline computing is employed to handle multiple input arrays at high speed. The hardware target is to employ multiple high-end FPGAs to process the combined FDAS module. The results show interesting consequences, where the best individual solutions are not necessarily the best solutions for the speed of a pipeline where FPGA resources and memory bandwidth need to be shared. By proposing multiple buffering techniques to the pipeline, the combined FDAS module can achieve up to 2[Formula: see text] speedup over implementations without pipeline computing. We perform an extensive experimental evaluation on multiple high-end FPGA cards hosted in a workstation and compare to a technology comparable mid-range GPU.

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