scholarly journals Verification of Wishbone Bus Interface for SoC using System Verilog and UVM

Author(s):  
Pooja. D. R

The Verification phase carries important role in design cycle of a system on chip. Verification gives with the actual enactment and functionality of a DUT and to verify the design meets the system requirements. This paper present wishbone bus interface for soc integration to interconnect architecture for portable IP cores and test bench is developed in system Verilog and verification is done by both system Verilog verification methodology and universal verification methodology which includes scoreboard, functional coverage and assertion. This paper based on two application to integrate IP cores that is single master with single slave interconnection and single master with multiple slave interconnections where master is test bench and slave will be a core.

Author(s):  
Erwin Setiawan ◽  
Trio Adiono ◽  
Syifaul Fuada

In this paper, we report a System-on-Chip (SoC) architecture for OFDM-based Visible Light Communication (VLC). The OFDM block was implemented as VLC PHY layer. The OFDM block comprises of transmitter and receiver. In transmitter block, there are Reed-Solomon encoder, modulator, IFFT, and preamble generator. While in receiver block, there are Reed-Solomon decoder, demodulator, FFT, and synchronizer. In SoC, these blocks are designed as IP cores. The industry standard AXI4-Stream protocol was used for data exchange between IP cores. The OFDM model in SoC was verified by comparing with a MATLAB simulation.


2018 ◽  
Vol 7 (2.16) ◽  
pp. 57
Author(s):  
G Prasad Acharya ◽  
M Asha Rani

The increased demand for processor-level parallelism has many-folded the challenges for SoC designers to design, simulate and verify/validate today’s Multi-core System-On-Chip (SoC) due to the increased system complexity. There is also a need to reduce the design cycle time to produce a complex multi-core SOC system thereby the product can be brought into the market within an affordable time. The Computer-Aided Design (CAD) tools and Field Programmable Gate Arrays (FPGAs) provide a solution for rapidly prototyping and validating the system. This paper presents an implementation of multi-core SoC consisting of 6 Xilinx Micro-Blaze soft-core processors integrated to the Zynq Processing System (PS) using IP Integrator and these cores will be communicated through AXI bus. The functionality of the system is verified using Micro-Blaze system debugger. The hardware framework for the implemented system is implemented and verified on FPGA.  


2013 ◽  
Vol 2013 ◽  
pp. 1-12 ◽  
Author(s):  
Mariem Turki ◽  
Zied Marrakchi ◽  
Habib Mehrez ◽  
Mohamed Abid

Multi-FPGA hardware prototyping is becoming increasingly important in the system on chip design cycle. However, after partitioning the design on the multi-FPGA platform, the number of inter-FPGA signals is greater than the number of physical connections available on the prototyping board. Therefore, these signals should be time-multiplexed which lowers the system frequency. The way in which the design is partitioned affects the number of inter-FPGA signals. In this work, we propose a set of constraints to be taken into account during the partitioning task. Then, the resulting inter-FPGA signals are routed with an iterative routing algorithm in order to obtain the best multiplexing ratio. Indeed, signals are grouped and then routed using the intra-FPGA routing algorithm: Pathfinder. This algorithm is adapted to deal with the inter-FPGA routing problem. Many scenarios are proposed to obtain the most optimized results in terms of prototyping system frequency. Using this technique, the system frequency is improved by an average of 12.8% compared to constructive routing algorithm.


Author(s):  
Janardhana S Y

The project aims to verify the AMBA AHB protocol by using universal verification methodology is presented in this paper. Advanced high-performance(AHB) is used for communication of on chip bus which support single clock edge operation wider data 32/64/128 bit can be supported. The new verification constructs can be easily reused for the objected-oriented feature of universal verification methodology (UVM). Verification IP is the one which provides a smart way to verify the AHB Components. The advanced verification testbench incorporates the illustrations regarding simulation result are analysed to evaluate the effectiveness of the proposed testbench and functional coverage is to check functionality of the design. The self-checking mechanism using assertions improves the quality of UVM check by shortening time to debug and reducing time to cover for the in-depth understanding of test case output.


2019 ◽  
pp. 28-32

Desarrollo e implementación de la interface SBA para un núcleo pWM de 16 canales independientes programables Development and implementation of the SBA interface for a 16 independent programmable channels pWM Ip Core Renzo Bermúdez y Miguel Risco Centro de Investigación y Desarrollo en Ingeniería (CIDI) de la Facultad de Ingeniería Electrónica y Mecatrónica Universidad Tecnológica del perú DOI: https://doi.org/10.33017/RevECIPeru2010.0017/ RESUMEN Los Ip-Cores (Núcleos de propiedad Intelectual) son para el diseño de hardware lo que las librerías son para la programación de computadoras. Se suelen utilizar en la forma de un circuito discreto integrado, donde la “placa de circuito” es un diseño más grande en ASIC o en FpGA. Un núcleo de propiedad intelectual a menudo adopta la forma de un programa de computadora escrito en el HDL, tales como Verilog, VHDL o SystemC. Idealmente, un Ip-Core debe ser totalmente “portable”, es decir, que fácilmente se pueda adaptar a cualquier tecnología de otros proveedores o diferentes métodos de diseño. Los Receptores/Transmisores Asíncronos Universales (UART), las Unidades Centrales de procesamiento (CpU), los Controladores Ethernet, las Interfaces pCI, son algunos ejemplos de Ip-Cores. En este trabajo, se presenta la adaptación de un IpCore pWM de 16 canales a una estructura de bloques independientes similar a los SoC (System on Chip). No se ha implementado un microprocesador como maestro del sistema; en su lugar una máquina de estado compleja administra un bus con la finalidad de ahorrar recursos en la FpGA. Esta máquina de estado compleja, que hace las veces de controlador del sistema, se encuentra dentro de una disposición a la que se le denomina SBA (Simple Bus Architecture) o Arquitectura Simple de Bus, la cual no es más de una simplificación de las señales y reglas que establece la especificación Wishbone. El sistema así integrado permite la configuración de 16 salidas digitales pWM independientes en modo de bajo rizado. Si bien en el ejemplo que se presenta en este trabajo muestra un solo IpCore pWM instanciado, esto no supone un límite. El núcleo pWM implementado no hace uso de recursos específicos o especiales de la FpGA, lo que permite que la cantidad de bloques instanciados pueda crecer tanto como bloques genéricos configurables en la FpGA se encuentren disponibles. Es decir, por cada núcleo instanciado se dispondrá de 16 canales pWM independientes que poseerán una posición de programación específica dentro del mapa de direcciones del SBA. Descriptores: FPGa, PWm, system on chip. ABSTRACT iP cores (intellectual Property cores) are for hardware design what libraries are for computer programming. They are typically used in the style and form of a discrete integrated circuit, where the “circuit board” is a larger design in asic or FPGa. a core intellectual property often takes the form of a software program written in hDl such as verilog, vhDl or systemc. ideally, an iP-core must be fully portable, meaning that it can be easily adapted to any technology from other suppliers or different design methods. receivers/transmitters universal asynchronous (uart), central Processing units (cPu), ethernet controllers, interfaces Pci are examples of iP-cores. This paper presents the adaptation of a 16-channel PWm iPcore to a separate brick structure similar to soc (system on chip). We did not implement a microprocessor as master of the system, instead a complex state machine runs a bus in order to save resources in the FPGa. This complex state machine that acts as the controller of the system is within a provision which is called sba (single bus architecture), which is just a simplification of the signals and rules establishing the Wishbone specification. The system thus allows the configuration of 16 independent PWm digital outputs in low ripple mode. While the example presented in this work shows a single PWm iPcore instantiated this is not a limit. The implemented PWm core does not use specific or special resources of the FPGa, which allows that the number of instantiated blocks can grow as much as configurable generic blocks in the FPGa become available. That is, for each instantiated core there will be 16 independent PWm channels that will have specific preset positions within the address map of the sba. Keywords: FPGa, PWm, system on chip.


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