Improved NOAA-20 Visible Infrared Imaging Radiometer Suite Day/Night Band Image Quality by Upgraded Gain Calibration

Due to complex radiometric calibration, the imagery collected by the Day/Night Band (DNB) of the Visible Infrared Imaging Radiometer Suite (VIIRS) onboard the Suomi National Polar Partnership (Suomi-NPP) and the NOAA-20 follow-on satellite is subject to artifacts such as striping, which eventually affect Earth remote sensing applications. Through comprehensive analysis using the NOAA-20 VIIRS DNB prelaunch-test and on-orbit data, it is revealed that the striping results from flaws in the calibration process. In particular, a discrepancy between the low-gain stage (LGS) Earth view (EV) gain and the onboard calibrator solar diffuser view gain makes the operational LGS gain coefficients of a few aggregation modes and detectors biased. Detector nonlinearity at low radiance level also induces errors to the mid-gain stage (MGS) and high-gain stage (HGS) gain through the biased gain ratios. These systematic errors are corrected by scaling the operational LGS gains using the factors derived from the NOAA-20 VIIRS DNB prelaunch test data and by adopting linear regression for evaluating the gain ratios. Striping in the NOAA-20 VIIRS DNB imagery is visibly reduced after the upgraded gain calibration process was implemented in the operational calibration.

IDeF-X HD: A CMOS ASIC for the Readout of Cd(Zn)Te Detectors for Space-Borne Applications

IDeF-X HD is a 32-channel analog front-end with self-triggering capability optimized for the readout of [Formula: see text] pixels CdTe or CdZnTe pixelated detectors to build a low power micro-gamma camera. IDeF-X HD has been designed in the standard AMS CMOS 0.35[Formula: see text][Formula: see text]m process technology. Its power consumption is 800[Formula: see text][Formula: see text]W per channel. The energy range of the ASIC can be extended to 1.1[Formula: see text]MeV thanks to the in-channel adjustable gain stage. When no detector is connected to the chip and without input current, a 33 electrons rms ENC level is achieved after shaping with 10.7[Formula: see text][Formula: see text]s peaking time. Spectroscopy measurements have been performed with CdTe Schottky detectors. We measured an energy resolution of 4.2[Formula: see text]keV FWHM at 667[Formula: see text]keV ([Formula: see text]Cs) on a single-pixel configuration. Meanwhile, we also measured 562[Formula: see text]eV and 666[Formula: see text]eV FWHM at 14[Formula: see text]keV and 60[Formula: see text]keV, respectively ([Formula: see text]Am) with a 256 small pixel array and a low detection threshold of 1.2[Formula: see text]keV. Since IDeF-X HD is intended for space-borne applications in astrophysics, we evaluated its radiation tolerance and its sensitivity to single event effects. We demonstrated that the ASIC remained fully functional without significant degradation of its performances after 200 krad and that no single event latch-up was detected putting the linear energy transfer threshold above 110[Formula: see text]MeV/(mg/cm2). Good noise performance and radiation tolerance make the chip well suited for X-rays energy discrimination and high energy resolution. The chip is space qualified and flies on board of the solar orbiter ESA mission launched in 2020.

Design of a CMOS Lineal Hall Sensor Front-End Working in Current Mode with Programmable Gain Stage for Power Specific Chip

With the continuous intelligentization of power systems, the demand for the integration of digital chips and sensor chips such as the Internet of Things is also increasing. A CMOS lineal magnetic Hall sensor front-end working in current mode with programmable gain stage is designed and implemented with SMIC 55 nm standard CMOS technology. By using a spinning-current technique, chopper technique, and digital calibration technique to eliminate the offset voltage and nonlinearity, this magnetic Hall sensor can be easily integrated into digital systems like SoCs. This work has already finished the circuit simulation and layout design, and all simulation indicators basically reach the expected value. The maximum gain of proposed sensor systems can be up to 33.9 dB. The total power is less than 4 mW. And the total area is less than 0.113 μm2. The magnetic Hall sensor can be easily integrated into chips such as the power Internet of Things to form a single-chip-level SoC design, which is mainly used in applications such as circuit breakers and electric energy measurement.

A Nano-Power 0.5 V Event-Driven Digital-LDO with Fast Start-Up Burst Oscillator for SoC-IoT

Towards the integration of Digital-LDO regulators in the ultra-low-power System-On-Chip Internet-of-Things architecture, the D-LDO architecture should constitute the main regulator for powering digital and mixed-signal loads including the SoC system clock. Such an implementation requires an in-regulator clock generation unit that provides an autonomous D-LDO design. In contrast to contemporary D-LDO designs that employ ring-oscillator architecture which start-up time is dependent on the oscillating frequency, this work presents a design with nano-power consumption, fabricated with an active area of 0.035 mm2 at a 55-nm Global Foundries CMOS process that introduces a fast start-up burst oscillator based on a high-gain stage with wake-up time independent of D-LDO frequency. In combination with linear search coarse regulation and asynchronous fine regulation, it succeeds 558 nA minimum quiescent current with CL 75 pF, maximum current efficiency of 99.2% and 1.16x power efficiency improvement compared to analog counterpart oriented to SoC-IoT loads.

An Approach for a Wide Dynamic Range Low-Noise Current Readout Circuit

Designing low-noise current readout circuits at high speed is challenging. There is a need for preamplification stages to amplify weak input currents before being processed by conventional integrator based readout. However, the high current gain preamplification stage usually limits the dynamic range. This article presents a 140 dB input dynamic range low-noise current readout circuit with a noise floor of 10 fArms/sq(Hz). The architecture uses a programmable bidirectional input current gain stage followed by an integrator-based analog-to-pulse conversion stage. The programmable current gains setting enables one to achieve higher overall input dynamic range. The readout circuit is designed and in 0.18 μm CMOS and consumes 10.3 mW power from a 1.8 V supply. The circuit has been verified using post-layout simulations.

Study on the thermal kinetics of anthracite oxidation induced by water and associated pyrite

Pyrite and water in coal have considerable influence on coal spontaneous combustion and threaten the safety of mine production gravely. To reveal the influence mechanism of water and associated pyrite on oxidation kinetics of coal–oxygen composite reaction, the pyrite of 0%, 1%, 2%, 4%, 6% and the moisture of 1%, 5%, 10%, 15% and 20% were mixed with the coal samples to obtain 25 coal samples. Thermogravimetric analysis technology was conducted to explore the changes of mass and characteristic temperatures of coal samples treated with water and associated pyrite during the low–temperature oxidation, and kinetic analysis of the oxidation process was discussed based on multiple heating rates(5 °C/min, 10 °C/min and15 °C/min).The results show that water and associated pyrite had a great influence on coal in oxygen absorption and weight gain stage ( T 3 ~ T 5 ), and there was a proportion range with the largest synergistic oxidation contribution. The apparent activation energy of the coal sample appeared changes, but the mechanism model did not, indicating that water and pyrite could affect the oxidation process of the coal sample externally. When water and associated pyrite exhibit synergistic interaction, there have a range that water was 10~15% and associate pyrite was 2~4% had the largest promotion and contribution to anthracite oxidation. The results have important scientific value and practical guiding significance for the further study on prediction, prevention and control of high sulfur anthracite spontaneous combustion.

A 10-bit 150MS/s Pipelined ADC with 2.5bit Gain Stage for High Frequency Applications

This paper proposes a 10-bit pipelined Analog to Digital Converter (ADC) which incorporates various techniques for lesser power and higher performance. The proposed method reduces the computational burden while comparing to the modified Monte-Carlo (MC) method. Pipelined ADC has N number of stages, it has higher resolution and higher frequency of conversion while comparing to other ADCs. The proposed ADC employs five 2.5bit gain stages; instead of 1.5bit gain stages for high accuracy. This method is implemented in the Tanner Software with the Generic 250nm library at a maximum power supply of 5V. The maximum frequency attained is 150MHz; and the ADC exhibits a SNR of 61.96dB. It also attains a 10bits as effective number of bits at the maximum sampling rate.