AN ENERGY EFFICIENT SECOND-ORDER ΣΔ MODULATOR BASED ON THE POWER AND DELAY OPTIMIZATION OF CBSC IIR FILTER

2012 ◽  
Vol 21 (08) ◽  
pp. 1240024
Author(s):  
MEHDI TAGHIZADEH ◽  
AMMAR RAHIMI KAZEROONI ◽  
MAJID ZAMANI ◽  
PAYMAN GOODARZI
Keyword(s):  
Dynamic Range ◽  
Second Order ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Iir Filter ◽  
Op Amps ◽  
Sampling Ratio ◽  
And Performance ◽  
Σδ Modulator ◽  
Gain Stage

In this paper a second-order low distortion Sigma-Delta Modulator (ΣΔM) with utilization of Comparator-Based Switched-Capacitor (CBSC)-based IIR filter, is explored. The advantages of this new structure are justified by the reduction of power and area. For this purpose IIR filter block can be made with single CBSC gain stage that has the same accuracy and performance of second-order filter with two Op-amps. The design of CBSC gain stages is intended to minimize the power consumption, and maximize Modulator performance. As shown in the simulation result, for a 20-KHz signal bandwidth, the modulator achieves a dynamic range of 70.2 dB and a peak signal-to-noise and distortion ratio (SNDR) of 68 dB with an over-sampling ratio of 64. In addition it consumes only 198 μW from a 1.8-V power supply at 2.56 MS/s.

scholarly journals Second-order sigma-delta modulator in standard cmos technology

2004 ◽  
Vol 1 (3) ◽  
pp. 37-44 ◽  
Author(s):  
Dragisa Milovanovic ◽  
Milan Savic ◽  
Miljan Nikolic
Keyword(s):  
Dynamic Range ◽  
Cmos Technology ◽  
Second Order ◽  
Clock Frequency ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Power Meter ◽  
Sampling Ratio

As a part of wider project sigma-delta modulator was designed. It represents an A/D part of a power meter IC. Requirements imposed were: SNDR and dynamic range > 50 dB for maximum input swing of 250 mV differential at 50 Hz. Over sampling ratio is 128 with clock frequency of 524288 Hz which gives bandwidth of 2048 Hz. Circuit is designed in 3.3 V supply standard CMOS 0.35 ?m technology.

A High-Performance Mash Fourth-Order Sigma-Delta Modulator

2012 ◽  
Vol 503 ◽  
pp. 207-210
Author(s):  
Wen Yan Liu ◽  
Bin Zhang ◽  
Long Chen ◽  
Chao Gao ◽  
Xiao Wei Liu
Keyword(s):  
Fourth Order ◽  
High Performance ◽  
System Stability ◽  
Quantization Noise ◽  
System Level ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
System Level Simulation ◽  
Sampling Ratio ◽  
Σδ Modulator

This paper reports on a system level design and analysis of a mash fourth-order sigma-delta (ΣΔ) modulator. Compared with a high-order single-loop ΣΔ modulator (ΣΔM), there’s no need to consider about the system stability of a mash ΣΔM, which has the advantages of better signal to quantization noise ratio (SQNR). System level simulation results indicate that the SQNR is 122.0 dB, and the effective number of bits (ENOB) is 19.97 bits when the over sampling ratio (OSR) is 128.

scholarly journals Second-order Sigma-Delta Modulator for Mobile BMIC Applications

2014 ◽  
Vol 18 (2) ◽  
pp. 263-271
Author(s):  
Chulkyu Park ◽  
Kichang Jang ◽  
Hyojae Kim ◽  
Joongho Choi
Keyword(s):  
Second Order ◽  
Sigma Delta Modulator ◽  
Sigma Delta

1V supply 16-bit second order Sigma-Delta modulator in a 90nm CMOS process

2012 ◽  
Author(s):  
Rochelle Marie F. Amistoso ◽  
Michael Joe A. Bautista ◽  
Rafael Karlo D.P. Delos Santos ◽  
Joana Rochelle R. Ortiz ◽  
Louis P. Alarcon ◽  
...  
Keyword(s):  
Second Order ◽  
Cmos Process ◽  
Sigma Delta Modulator ◽  
Sigma Delta

A 3.3 V, 10 Bits, Clock-Feedthrough Compensated Switched-Current Second Order Sigma-Delta Modulator

2004 ◽  
Vol 39 (1) ◽  
pp. 81-87 ◽  
Author(s):  
Mourad Loulou ◽  
Dominique Dallet ◽  
Nouri Masmoudi ◽  
Philippe Marchegay ◽  
Lotfi Kamoun
Keyword(s):  
Second Order ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Clock Feedthrough ◽  
Switched Current
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