The Internal and the External Clock

2021 ◽  
pp. 404-422
Keyword(s):  
External Clock

Low Power Design of a 1 V 8-bit 125 fJ Asynchronous SAR ADC with Binary Weighted Capacitive DAC

2017 ◽  
Vol 26 (05) ◽  
pp. 1750077 ◽  
Author(s):  
Anush Bekal ◽  
Shabi Tabassum ◽  
Manish Goswami
Keyword(s):  
Low Power ◽  
Successive Approximation ◽  
Digital Control ◽  
Low Power Design ◽  
Cmos Technology ◽  
Control Logic ◽  
Control Block ◽  
Logic Block ◽  
External Clock ◽  
Asynchronous Sar

The work proposes an improved technique to design a low power 8-bit asynchronous successive approximation register (ASAR), an analog-to-digital converter (ADC). The proposed ASAR ADC consists of a comparator, ASAR (digital control logic block), and a capacitive-digital-to-analog convertor (C-DAC). The comparator is a preamplier-based improved positive feedback latch circuit which has a built-in sample and hold (S/H) functionality and saves an enormous amount of power. The implemented digital control logic block performing the successive approximation (SA) algorithm is totally unrestrained of the external clock pulse. The outputs from the comparator are given to a XOR logic whose outputs serve as an internally generated clock (ready signal) to trigger the digital control block. Hence, an external clock is not required to initiate the digital control block making its operation asynchronous. By implementing this, the ADC can circumvent the usage of an oversampled clock and can operate on a single low-speed sample clock. This, in turn, saves power and it cuts down the required resilience in sampling rates. The proposed ADC has been designed and simulated using UMC-0.18[Formula: see text][Formula: see text]m CMOS technology which dissipates 32.18[Formula: see text][Formula: see text]W power when operated on a single 1[Formula: see text]V power supply and achieves complete 8-bit conversion in 1.09[Formula: see text][Formula: see text]s. The relative accuracy of capacitor ratio, aperture jitter and FOM are 0.39[Formula: see text], 1.2[Formula: see text]ns and 125[Formula: see text]fJ/conversion-step, respectively.

scholarly journals Mass-correlated rotational Raman spectra with high resolution, broad bandwidth, and absolute frequency accuracy

2018 ◽  
Vol 115 (20) ◽  
pp. 5072-5076 ◽  
Author(s):  
Christian Schröter ◽  
Jong Chan Lee ◽  
Thomas Schultz
Keyword(s):  
Raman Spectra ◽  
Optical Excitation ◽  
Rotational Transition ◽  
Observation Time ◽  
Absolute Frequency ◽  
Naturally Occurring ◽  
Order Of Magnitude ◽  
Quantum Wave ◽  
External Clock ◽  
Time And Energy

We present mass-correlated rotational alignment spectroscopy, based on the optical excitation of a coherent rotational quantum wave and the observation of temporal wave interferences in a mass spectrometer. Combined electronic and opto-mechanical delays increased the observation time and energy resolution by an order of magnitude compared with preceding time-domain measurements. Rotational transition frequencies were referenced to an external clock for accurate absolute frequency measurements. Rotational Raman spectra for six naturally occurring carbon disulfide isotopologues were resolved with 3 MHz resolution over a spectral range of 500 GHz. Rotational constants were determined with single-kilohertz accuracy, competitive with state-of-the-art frequency domain measurements.

scholarly journals Temporal-imaging system with simple external-clock triggering

2010 ◽  
Vol 18 (13) ◽  
pp. 14262 ◽  
Author(s):  
Daniel H. Broaddus ◽  
Mark A. Foster ◽  
Onur Kuzucu ◽  
Amy C. Turner-Foster ◽  
Karl W. Koch ◽  
...  
Keyword(s):  
Imaging System ◽  
External Clock

On the Computational Complexity of Binary and Analog Symmetric Hopfield Nets

2000 ◽  
Vol 12 (12) ◽  
pp. 2965-2989 ◽  
Author(s):  
Jiří Šíma ◽  
Pekka Orponen ◽  
Teemu Antti-Poika
Keyword(s):  
Computation Time ◽  
Network Size ◽  
Linear Increase ◽  
Convergence Time ◽  
Polynomial Time Approximation Algorithm ◽  
Asymmetric Networks ◽  
External Clock ◽  
Binary Networks ◽  
Computational Properties ◽  
Symmetric Networks

We investigate the computational properties of finite binary- and analog-state discrete-time symmetric Hopfield nets. For binary networks, we obtain a simulation of convergent asymmetric networks by symmetric networks with only a linear increase in network size and computation time. Then we analyze the convergence time of Hopfield nets in terms of the length of their bit representations. Here we construct an analog symmetric network whose convergence time exceeds the convergence time of any binary Hopfield net with the same representation length. Further, we prove that the MIN ENERGY problem for analog Hopfield nets is NP-hard and provide a polynomial time approximation algorithm for this problem in the case of binary nets. Finally, we show that symmetric analog nets with an external clock are computationally Turing universal.

Improving OFDR spatial resolution by reducing external clock sampling error

2016 ◽  
Vol 363 ◽  
pp. 74-79 ◽  
Author(s):  
Bowen Feng ◽  
Kun Liu ◽  
Tiegen Liu ◽  
Junfeng Jiang ◽  
Yang Du
Keyword(s):  
Spatial Resolution ◽  
Sampling Error ◽  
External Clock

High Speed Min/Max Architecture Based on a Novel Comparator in 0.18-μm CMOS Process

2015 ◽  
Vol 24 (04) ◽  
pp. 1550048 ◽  
Author(s):  
Amir Fathi ◽  
Abdollah Khoei ◽  
Khayrollah Hadidi
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Current Mode ◽  
Cmos Technology ◽  
Operating Frequency ◽  
Cmos Process ◽  
Fuzzy Logic Controllers ◽  
Speed Performance ◽  
External Clock ◽  
Frequency Feature

This paper describes the design of a high speed min/max architecture based on a new current comparator. The main advantage of the proposed circuit which employs a novel preamplifier-latch comparator is the higher operating frequency feature in comparison with previous works. Because the comparator can work in voltage mode, the min/max structure can be redesigned either in voltage or current mode. The designed comparator is refreshed without any external clock. Therefore, it does not degrade the speed performance of proposed min/max structure. These features along with low power consumption qualify the proposed architecture to be widely used in high speed fuzzy logic controllers (FLCs). Post-layout simulation results confirm 3.4 GS/s comparison rate with 9-bit resolution for a 0.9 V peak-to-peak input signal range for the comparator and 800 MHz operating frequency for min/max circuit. The power consumption of whole structure is 912 μW from a 1.8 V power supply using TSMC 0.18-μm CMOS technology.

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