A S-band 3D Surface Mount Packaged SiGe and GaN Tx Module Using Flip-Chip Bonding and a Device Embedded PCB Substrate

Author(s):  
Kengo Kawasaki ◽  
Eigo Kuwata ◽  
Hidenori Ishibashi ◽  
Tomohiro Yao ◽  
Kiyoshi Ishida ◽  
...  
Author(s):  
Kengo Kawasaki ◽  
Eigo Kuwata ◽  
Hidenori Ishibashi ◽  
Tomohiro Yao ◽  
Kiyoshi Ishida ◽  
...  

2002 ◽  
Author(s):  
Ronald E. Reedy ◽  
Hal Anthony ◽  
Charles Kuznia ◽  
Mike Pendelton ◽  
Jim Cable ◽  
...  

Author(s):  
Jin Yang ◽  
Charles Ume

Microelectronics packaging technology has evolved from through-hole and bulk configuration to surface-mount and small-profile ones. In surface mount packaging, such as flip chips, chip scale packages (CSP), and ball grid arrays (BGA), chips/packages are attached to the substrates or printed wiring boards (PWB) using solder bump interconnections. Solder bumps, which are hidden between the device and the substrate/board, are no longer visible for inspection. A novel solder bump inspection system has been developed using laser ultrasound and interferometric techniques. This system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chips, and chip scale packages. This system uses a pulsed Nd:YAG laser to induce ultrasound in the thermoelastic regime and the transient out-of-plane displacement response on the device surface is measured using the interferometric technique. In this paper, local temporal coherence (LTC) analysis of laser ultrasound signals is presented and compared to previous signal processing methods, including Error Ratio and Correlation Coefficient. The results show that local temporal coherence analysis increases measurement sensitivity for inspecting solder bumps in packaged electronic devices. Laser ultrasound inspection results are also compared with X-ray and C-mode Scanning Acoustic Microscopy (CSAM) results. In particular, this paper discusses defect detection for a 6.35mm×6.35mm×0.6mm PB18 flip chip and a flip chip (SiMAF) with 24 lead-free solder bumps. These two flip chip specimens are both non-underfilled.


1999 ◽  
Author(s):  
Jianbiao Pan ◽  
Gregory L. Tonkay

Abstract Stencil printing has been the dominant method of solder deposition in surface mount assembly. With the development of advanced packaging technologies such as ball grid array (BGA) and flip chip on board (FCOB), stencil printing will continue to play an important role. However, the stencil printing process is not completely understood because 52–71 percent of fine and ultra-fine pitch surface mount assembly defects are printing process related (Clouthier, 1999). This paper proposes an analytical model of the solder paste deposition process during stencil printing. The model derives the relationship between the transfer ratio and the area ratio. The area ratio is recommended as a main indicator for determining the maximum stencil thickness. This model explains two experimental phenomena. One is that increasing stencil thickness does not necessarily lead to thicker deposits. The other is that perpendicular apertures print thicker than parallel apertures.


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