Design and Implementation of Fast Fourier Transform (FFT) using VHDL Code

2018 ◽  
Vol 6 (8) ◽  
pp. 268
Author(s):  
Akarshika Singhal ◽  
Anjana Goen ◽  
Tanu Trushna Mohapatrara
Keyword(s):  
Image Processing ◽  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Discrete Fourier Transform ◽  
Digital Signal ◽  
Frequency Division ◽  
Signal And Image Processing ◽  
Design And Implementation ◽  
Fft Processor ◽  
Vhdl Code

The Discrete Fourier Transform (DFT) can be implemented very fast using Fast Fourier Transform (FFT). It is one of the finest operation in the area of digital signal and image processing. FFT is a luxurious operation in terms of MAC. To achieve FFT calculation with a many points and with maximum number of samples the MACs requirement could not be matched by efficient hardware’s like DSP. A parallel and pipelined Fast Fourier Transform (FFT) processor for use in the Orthogonal Frequency division Multiplexer (OFDM) and WLAN, unlike being stored in the traditional ROM. The twiddle factors in our pipelined FFT processor can be accessed directly. In this paper, we present the implementation of fast algorithms for the DFT for evaluating their performance. The performance of this algorithm by implementing them on the Xillinx 9.2i Spartan 3E FPGAs  by developing our own FFT processor architecture.

scholarly journals Implementation of FFT Architecture using Various Adders

2019 ◽  
Vol 8 (10) ◽  
pp. 3750-3755
Keyword(s):  
Image Processing ◽  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Orthogonal Frequency Division Multiplex ◽  
Cell Phones ◽  
Frequency Division ◽  
Ripple Carry Adder ◽  
Significant Area ◽  
Area Optimization ◽  
The Fourier Transform

In 1965 a technique called Fast Fourier Transform (FFT) was invented to find the Fourier Transform. This paper compares three architectures, the basic architecture/ non-reduced architecture of FFT, decomposed FFT architecture without retiming and decomposed FFT architecture with retiming. In each case, the adder used will be Ripple Carry Adder (RCA) and Carry Save Adder (CSA). A fast Fourier transform (FFT) calculates the discrete Fourier transform (DFT) or the inverse (IDFT) of a sequence. Fourier analysis transforms a signal from time to frequency domain or vice versa. One of the most burgeoning use of FFT is in Orthogonal Frequency Division Multiplex (OFDM) used by most cell phones, followed by the use in image processing. The synthesis has been carried out on Xilinx ISE Design Suite 14.7. There is a decrease in delay of 0.824% in Ripple Carry Adder and 6.869% in Carry Save Adder, further the reduced architecture for both the RCA and CSA architectures shows significant area optimization (approximately 20%) from the non-reduced counterparts of the FFT implementation.

scholarly journals Comparison of Discrete Fourier Transform and Fast Fourier Transform with Reduced Number of Multiplication and Addition Operations

2020 ◽  
Vol Volume 14 ◽  
Keyword(s):  
Signal Processing ◽  
Fourier Transform ◽  
Digital Signal Processing ◽  
Fast Fourier Transform ◽  
Discrete Fourier Transform ◽  
Symmetry Property ◽  
Digital Signal ◽  
Basic Structure ◽  
Phase Factor ◽  
Normal Order

Fast Fourier Transform is an advanced algorithm for computing Discrete Fourier Transform efficiently. Although the results available from the operation of Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT) are same, but exploiting the periodicity and symmetry property of phase factor Fast Fourier Transform computes the Discrete Fourier Transform using reduced number of multiplication and addition operations. The basic structure used in the operations of Fast Fourier Transform is the Butterfly structure. For the implementation of Fast Fourier Transform the two methods are used such as decimation in time (DIT) and decimation in frequency (DIF). Both the methods give same result but for decimation in time of Fast Fourier Transform bit reversed inputs are applied and for decimation in frequency of Fast Fourier Transform normal order inputs are applied, and the result is reversed again. In this paper, operations for DFT and FFT have been discussed and shown with examples. It is found that generalized formula for FFT have been described same in the books, but the expressions in the intermediate computations for the first decimation and second decimation are different in the various books of Digital Signal Processing. The expressions in the intermediate computation of FFT described in different books are broadly compared in this paper

scholarly journals FFT Implementation using Modified Booth Multiplier and CLA

2020 ◽  
Vol 9 (3) ◽  
pp. 2780-2782
Keyword(s):  
Image Processing ◽  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Voice Recognition ◽  
Digital Signal ◽  
Efficient Design ◽  
Efficient Manner ◽  
Booth Multiplier ◽  
Hearing Devices ◽  
Recognition Systems

In the field of digital signal and image processing the Fast Fourier Transform (FFT) is one of the rudimentary operations. Telecommunication, Automotive, Hearing devices, Voice recognition systems are some of the applications of Fast Fourier Transform. DFT is implemented using FFT which is a type of algorithm that computes DFT in a fast and efficient manner. This project concentrates on the development of the Fast Fourier Transform (FFT), based on Decimation In Time (DIT) domain, Radix2 algorithm, using VHDL as a design entity.The objective of this project is to establish an efficient design that computes FFT in a faster way. In this project FFT is implemented using modified booth multiplier and CLA and simulated on Xilinx ISE.

scholarly journals Signal-to-noise Ratio Study on Pipelined Fast Fourier Transform Processor

2018 ◽  
Vol 7 (2) ◽  
pp. 230-235
Author(s):  
S. L. M. Hassan ◽  
N. Sulaiman ◽  
S. S. Shariffudin ◽  
T. N. T. Yaakub
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Signal To Noise Ratio ◽  
Data Communication ◽  
Digital Signal ◽  
Signal To Noise ◽  
Digital Video Broadcasting ◽  
Video Broadcasting ◽  
Fft Processor ◽  
Noise Ratio

Fast Fourier transform (FFT) processor is a prevailing tool in converting signal in time domain to frequency domain. This paper provides signal-to-noise ratio (SNR) study on 16-point pipelined FFT processor implemented on field-programable gate array (FPGA). This processor can be used in vast digital signal applications such as wireless sensor network, digital video broadcasting and many more. These applications require accuracy in their data communication part, that is why SNR is an important analysis. SNR is a measure of signal strength relative to noise. The measurement is usually in decibles (dB). Previously, SNR studies have been carried out in software simulation, for example in Matlab. However, in this paper, pipelined FFT and SNR modules are developed in hardware form. SNR module is designed in Modelsim using Verilog code before implemented on FPGA board. The SNR module is connected directly to the output of the pipelined FFT module. Three different pipelined FFT with different architectures were studied. The result shows that SNR for radix-8 and R4SDC FFT architecture design are above 40dB, which represent a very excellent signal. SNR module on the FPGA and the SNR results of different pipelined FFT architecture can be consider as the novelty of this paper.

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