scholarly journals A –5 dBm 400MHz OOK Transmitter for Wireless Medical Application

2014 ◽  
Vol 60 (2) ◽  
pp. 193-198
Author(s):  
M. Yousefi ◽  
D. Koozehkanani ◽  
H. Jangi ◽  
N. Nasirzadeh ◽  
J. Sobhi
Keyword(s):  
Energy Consumption ◽  
Power Amplifier ◽  
High Efficiency ◽  
Medical Application ◽  
Cmos Technology ◽  
High Energy ◽  
Data Rate ◽  
High Data Rate ◽  
Low Power Consumption ◽  
High Data

Abstract A 400 MHz high efficiency transmitter for wireless medical application is presented in this paper. Transmitter architecture with high-energy efficiencies is proposed to achieve high data rate with low power consumption. In the on-off keying transmitters, the oscillator and power amplifier are turned off when the transmitter sends 0 data. The proposed class-e power amplifier has high efficiency for low level output power. The proposed on-off keying transmitter consumes 1.52 mw at -5 dBm output by 40 Mbps data rate and energy consumption 38 pJ/bit. The proposed transmitter has been designed in 0.18μm CMOS technology.

A high data rate and high efficiency 60 GHz OOK demodulator in 90 NM CMOS

2017 ◽  
Vol 59 (5) ◽  
pp. 1081-1084
Author(s):  
Chul Woo Byeon ◽  
Chul Soon Park
Keyword(s):  
High Efficiency ◽  
Data Rate ◽  
High Data Rate ◽  
60 Ghz ◽  
High Data

Design of DQPSK Demodulator for Implantable Biomedical Devices

2020 ◽  
Vol 29 (11) ◽  
pp. 2020007
Author(s):  
Vaibhav Garg ◽  
Kavindra Kandpal
Keyword(s):  
Low Power ◽  
Carrier Frequency ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Vital Role ◽  
Data Rate ◽  
High Data Rate ◽  
Biomedical Devices ◽  
High Data ◽  
Implantable Biomedical Devices

Implantable biomedical devices (IBDs) play a vital role in today’s healthcare industry. Such applications demand high data rate, low power and small-sized demodulators. This work presents a simple small-sized low-power architecture for differential quadrature phase shift keying (DQPSK) demodulator for these devices. The proposed circuitry is designed in UMC 90-nm CMOS technology and occupies a layout area of 0.015[Formula: see text]mm2. It is operated at 1-V supply voltage with a power consumption of 405[Formula: see text][Formula: see text]W. The carrier frequency is 10[Formula: see text]MHz and the obtained data rate is 20[Formula: see text]Mbps. Hence it exhibits a high data-rate-to-carrier-frequency (DRCF) ratio of 200% making it ideal for IBDs.

PAPR REDUCTION IN MIMO SC-FDMA- A SURVEY

2015 ◽  
Vol 2 (2) ◽  
Author(s):  
HARSHA PRAKASH ◽  
C.D. SURIYAKALA
Keyword(s):  
Power Amplifier ◽  
Communication Systems ◽  
Multiple Access ◽  
Average Power ◽  
Data Rate ◽  
High Data Rate ◽  
Modulation Method ◽  
Frequency Division ◽  
High Data ◽  
Power Amplifier Efficiency

To meet the requirements of high data rate, third generation partnership project (3GPP) has come across the development of long term evolution (LTE). High data rate can be achieved with the help of an advanced modulation method. Orthogonal Frequency Division Multiple Access (OFDMA) was considered as a modulation method especially in the downlink of the communication systems. It gives many advantages like frequency diversity, increased capacity and robustness against impulse noise. Besides these advantages, a major drawback of OFDMA is its high peak-to-average power ratio (PAPR). High PAPR affects the system by lowering the power amplifier efficiency, increased complexity as well as shorter battery life. In case of uplink communication, where better peak power characteristics benefit the mobile terminals with respect to power efficiency, OFDMA is not a possible solution. To handle such situations, 3GPP has introduced a modified form of OFDMA which is known as Single-Carrier Frequency Division Multiple Access (SC-FDMA). It provides same advantages as OFDMA along with low PAPR. To further improve the bit error rate (BER) performance of the system and power amplifier efficiency Multiple-Input Multiple-Output (MIMO) can be extended to SC-FDMA system. This paper surveys causes, effects and possible solutions of high PAPR in a communication system.

Low power high data rate GHz range receiver in 40nm CMOS technology

2011 ◽  
Author(s):  
XiaoPeng Yu ◽  
ZhengHao Lu ◽  
Wei Meng Lim ◽  
Kiat Seng Yeo ◽  
Yang Liu ◽  
...  
Keyword(s):  
Low Power ◽  
Cmos Technology ◽  
Data Rate ◽  
High Data Rate ◽  
High Data
Sign in / Sign up

Export Citation Format

Share Document