scholarly journals A Cryptography Core Tolerant to DFA Fault Attacks

2007 ◽  
Vol 2 (1) ◽  
pp. 14-21
Author(s):  
Carlos R. Moratelli ◽  
Érika Cota ◽  
Marcelo S. Lubaszewski
Keyword(s):  
Fault Detection ◽  
Error Correction ◽  
Fault Injection ◽  
Smart Cards ◽  
Experimental Results ◽  
Transient Faults ◽  
Fault Attacks ◽  
Cryptographic Algorithms

This work describes a hardware approach for the concurrent fault detection and error correction in a cryptographic core. It has been shown in the literature that transient faults injected in a cryptographic core can lead to the revelation of the encryption key using quite inexpensive equipments. This kind of attack is a real threat to tamper resistant devices like Smart Cards. To tackle such attacks, the cryptographic core must be immune to transient faults. In this work the DES algorithm is taken as a vulnerable cryptosystem case study.We show how an attack against DES is performed through a fault injection campaign. Then, a countermeasure based on partial hardware replication is proposed and applied to DES. Experimental results show the efficiency of the proposed scheme to protect DES against DFA fault attacks. Furthermore, the proposed solution is independent of implementation, and can be applied to other cryptographic algorithms, such as AES.

scholarly journals Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2074
Author(s):  
J.-Carlos Baraza-Calvo ◽  
Joaquín Gracia-Morán ◽  
Luis-J. Saiz-Adalid ◽  
Daniel Gil-Tomás ◽  
Pedro-J. Gil-Vicente
Keyword(s):  
Fault Tolerance ◽  
Error Correction ◽  
Error Detection ◽  
Fault Injection ◽  
Error Correction Codes ◽  
Transient Faults ◽  
Tolerance Mechanism ◽  
Intermittent Faults ◽  
Risc Processor ◽  
Simulation Based

Due to transistor shrinking, intermittent faults are a major concern in current digital systems. This work presents an adaptive fault tolerance mechanism based on error correction codes (ECC), able to modify its behavior when the error conditions change without increasing the redundancy. As a case example, we have designed a mechanism that can detect intermittent faults and swap from an initial generic ECC to a specific ECC capable of tolerating one intermittent fault. We have inserted the mechanism in the memory system of a 32-bit RISC processor and validated it by using VHDL simulation-based fault injection. We have used two (39, 32) codes: a single error correction–double error detection (SEC–DED) and a code developed by our research group, called EPB3932, capable of correcting single errors and double and triple adjacent errors that include a bit previously tagged as error-prone. The results of injecting transient, intermittent, and combinations of intermittent and transient faults show that the proposed mechanism works properly. As an example, the percentage of failures and latent errors is 0% when injecting a triple adjacent fault after an intermittent stuck-at fault. We have synthesized the adaptive fault tolerance mechanism proposed in two types of FPGAs: non-reconfigurable and partially reconfigurable. In both cases, the overhead introduced is affordable in terms of hardware, time and power consumption.

scholarly journals Persistent Fault Analysis on Block Ciphers

2018 ◽  
pp. 150-172 ◽  
Author(s):  
Fan Zhang ◽  
Xiaoxuan Lou ◽  
Xinjie Zhao ◽  
Shivam Bhasin ◽  
Wei He ◽  
...  
Keyword(s):  
Time Synchronization ◽  
Fault Injection ◽  
Block Ciphers ◽  
Fault Analysis ◽  
Experimental Results ◽  
Fault Attacks ◽  
Intrinsic Nature ◽  
Fault Attack ◽  
Modular Redundancy

Persistence is an intrinsic nature for many errors yet has not been caught enough attractions for years. In this paper, the feature of persistence is applied to fault attacks, and the persistent fault attack is proposed. Different from traditional fault attacks, adversaries can prepare the fault injection stage before the encryption stage, which relaxes the constraint of the tight-coupled time synchronization. The persistent fault analysis (PFA) is elaborated on different implementations of AES-128, specially fault hardened implementations based on Dual Modular Redundancy (DMR). Our experimental results show that PFA is quite simple and efficient in breaking these typical implementations. To show the feasibility and practicability of our attack, a case study is illustrated on the shared library Libgcrypt with rowhammer technique. Approximately 8200 ciphertexts are enough to extract the master key of AES-128 when PFA is applied to Libgcrypt1.6.3 with redundant encryption based DMR. This work puts forward a new direction of fault attacks and can be extended to attack other implementations under more interesting scenarios.

Precise Cache Profiling for Studying Radiation Effects

2021 ◽  
Vol 20 (3) ◽  
pp. 1-25
Author(s):  
James Marshall ◽  
Robert Gifford ◽  
Gedare Bloom ◽  
Gabriel Parmer ◽  
Rahul Simha
Keyword(s):  
Radiation Effects ◽  
Fault Injection ◽  
Error Correcting Codes ◽  
Direct Access ◽  
Transient Faults ◽  
Large Area ◽  
Common Multiple ◽  
Single Event Upsets ◽  
On Chip ◽  
Future Work

Increased access to space has led to an increase in the usage of commodity processors in radiation environments. These processors are vulnerable to transient faults such as single event upsets that may cause bit-flips in processor components. Caches in particular are vulnerable due to their relatively large area, yet are often omitted from fault injection testing because many processors do not provide direct access to cache contents and they are often not fully modeled by simulators. The performance benefits of caches make disabling them undesirable, and the presence of error correcting codes is insufficient to correct for increasingly common multiple bit upsets. This work explores building a program’s cache profile by collecting cache usage information at an instruction granularity via commonly available on-chip debugging interfaces. The profile provides a tighter bound than cache utilization for cache vulnerability estimates (50% for several benchmarks). This can be applied to reduce the number of fault injections required to characterize behavior by at least two-thirds for the benchmarks we examine. The profile enables future work in hardware fault injection for caches that avoids the biases of existing techniques.

scholarly journals SOFTWARE IMPLEMENTED HARDWARE-TRANSIENT FAULTS DETECTION

2014 ◽  
pp. 26-30
Author(s):  
Goutam Kumar Saha
Keyword(s):  
Error Correction ◽  
Fault Tolerant ◽  
Low Cost ◽  
Transient Faults ◽  
Fault Tolerant System ◽  
Cost Approach ◽  
Run Time ◽  
Commodity Systems ◽  
Fail Safe ◽  
Register Error

This paper examines a software implemented self-checking technique that is capable of detecting processorregisters' hardware-transient faults. The proposed approach is intended to detect run-time transient bit-errors in memory and processor status register. Error correction is not considered here. However, this low-cost approach is intended to be adopted in commodity systems that use ordinary off-the-shelf microprocessors, for the purpose of operational faults detection towards gaining fail-safe kind of fault tolerant system.

scholarly journals Multiple Working Mode Based Door Opening Control and Fault Detection of Mobile Modular and Reconfigurable Robot

2021 ◽  
Author(s):  
Saleh Ahmad Ali
Keyword(s):  
Fault Detection ◽  
Control Design ◽  
Torque Control ◽  
Experimental Results ◽  
Joint Torque ◽  
Detection Scheme ◽  
Door Opening ◽  
Position Errors ◽  
Internal Forces ◽  
Reconfigurable Robot

The study in this thesis addresses the problem of opening a door with a modular and reconfigurable robot (MRR) mounted on a wheeled mobile robot platform. The foremost issue with door opening problems is the prevention of occurrence of large internal forces that arise due to position errors or imprecise modeling of the robot or its environment, i.e. the door parameters, specifically. Unlike previous methods that relied on compliance control, making the control design rather complicated, this thesis presents a new concept that utilizes the multiple working modes of the MRR modules. The control design is significantly simplified by switching selected joints of the MRR to work in passive mode during door opening operation. As a result, the occurrence of large internal forces is prevented. Different control schemes are used for control of the joint modules in different working modes. For passive joint modules, a feedforward torque control approach is used to compensate the joint friction to ensure passive motion. For the active joint modules, a distributed control method, based on torque sensing, is used to facilitate the control of joint modules working under this mode. To enable autonomous door opening, an online door parameter estimation algorithm is proposed on the basis of the least squares method; and a path planning algorithm is developed on the basis of Hermite cubic spline functions, with consideration of motion constraints of the mobile MRR. The theory is validated using simulations and experimental results, as presented herein. A distributed fault detection scheme for MRR robots with joint torque sensing is also proposed in this thesis. The proposed scheme relies on filtering the joint torque command and comparing it with a filtered torque estimate that is derived from the nonlinear dynamic model of MRR with joint torque sensing. Common joint actuator faults are considered with fault detection being performed independently for each joint module. The proposed fault detection scheme for each module does not require motion states of any other module, making it an ideal modular approach for fault detection of modular robots. Experimental results have attested the effectiveness of the proposed fault detection scheme.

scholarly journals Symmetric-Key Cryptographic Routine Detection in Anti-Reverse Engineered Binaries Using Hardware Tracing

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 957 ◽  
Author(s):  
Juhyun Park ◽  
Yongsu Park
Keyword(s):  
False Positive ◽  
False Positive Rate ◽  
Experimental Results ◽  
Software Implementation ◽  
Detection Scheme ◽  
Prototype Implementation ◽  
Cryptographic Algorithms ◽  
Positive Rate ◽  
Symmetric Key

Software uses cryptography to provide confidentiality in communication and to provide authentication. Additionally, cryptographic algorithms can be used to protect software against cracking core algorithms in software implementation. Recently, malware and ransomware have begun to use encryption to protect their codes from analysis. As for the detection of cryptographic algorithms, previous works have had demerits in analyzing anti-reverse engineered binaries that can detect differences in analysis environments and normal execution. Here, we present a new symmetric-key cryptographic routine detection scheme using hardware tracing. In our experiments, patterns were successfully generated and detected for nine symmetric-key cryptographic algorithms. Additionally, the experimental results show that the false positive rate of our scheme is extremely low and the prototype implementation successfully bypasses anti-reversing techniques. Our work can be used to detect symmetric-key cryptographic routines in malware/ransomware with anti-reversing techniques.

scholarly journals Integration of Convolutional Neural Network and Error Correction for Indoor Positioning

2020 ◽  
Vol 9 (2) ◽  
pp. 74
Author(s):  
Eric Hsueh-Chan Lu ◽  
Jing-Mei Ciou
Keyword(s):  
Neural Network ◽  
Convolutional Neural Network ◽  
Error Correction ◽  
Spatial Information ◽  
Rapid Development ◽  
Indoor Positioning ◽  
Experimental Results ◽  
Global Navigation Satellite Systems ◽  
Signal Interference ◽  
Position Vector

With the rapid development of surveying and spatial information technologies, more and more attention has been given to positioning. In outdoor environments, people can easily obtain positioning services through global navigation satellite systems (GNSS). In indoor environments, the GNSS signal is often lost, while other positioning problems, such as dead reckoning and wireless signals, will face accumulated errors and signal interference. Therefore, this research uses images to realize a positioning service. The main concept of this work is to establish a model for an indoor field image and its coordinate information and to judge its position by image eigenvalue matching. Based on the architecture of PoseNet, the image is input into a 23-layer convolutional neural network according to various sizes to train end-to-end location identification tasks, and the three-dimensional position vector of the camera is regressed. The experimental data are taken from the underground parking lot and the Palace Museum. The preliminary experimental results show that this new method designed by us can effectively improve the accuracy of indoor positioning by about 20% to 30%. In addition, this paper also discusses other architectures, field sizes, camera parameters, and error corrections for this neural network system. The preliminary experimental results show that the angle error correction method designed by us can effectively improve positioning by about 20%.

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