Test and Failure Analysis Implications of a Novel Inter-Bit Dependency in a Non-Volatile Memory

Failure analysis of non-volatile memory arrays can be complicated by the history of bits elsewhere in the array. This generally is in contrast to volatile memories, in which the state of all bits can quickly be reset by over-writing the bits, or by simply removing power from the array. On one of our products, EEPROM bits failed to program if certain patterns of bits were programmed elsewhere in the EEPROM array. During programming, high voltages (>18 volts) are present within the EEPROM array. Such voltage levels caused a narrow field oxide region to break down, thereby pulling down the programming voltage and preventing the successful programming of EEPROM transistors. What complicated the analysis, however, was that the breakdown only occurs if a checkerboard pattern is being programmed in one part of the array, while specific other EEPROM bits had previously been programmed elsewhere in the array. Until the failure mechanism was well understood, electrical screens were difficult to implement, because they typically do not account for complicated interactions between bits. This is especially true for nonvolatile memories, for which test time costs often prohibit the use of complicated test patterns with improved test coverage. This paper reviews the failure analysis, and proceeds to highlight the importance of knowing the contents of nonvolatile arrays prior to performing either failure analysis or automated testing on such an array. The case study therefore applies to both test and failure analysis engineers.