Universal Service Systems for Scalable Copper Packaging of Discrete Circuit Components

In the decade of digital electronics, no matter what type is, high-value, high-complexity, high-performance devices (such as the main microprocessor core in smart phones) is undoubtedly crucial. However, simple discrete circuit components (such as capacitors, resistors, diodes, transistors, etc.) are also essential for mobile phones. In order to continue to increase functionality and reliability, reduce size and power consumption, reduce costs, and any function we seek in electronic equipment, there is always the basic principle of squeezing everything onto the same semiconductor chip. However, in some unavoidable situations, not all circuit components can run on the same chip. This service system uses a copper substrate as the core material for packaging, and can package chips with high bonding density. It provides a universal service platform for packaged products called: Scalable Universal Copper-based Packaging (CopperPak) service system. This service system is attributed to copper-based packaging (CopperPak) as a solution for expansion packaging, which can package the chip on the multifunctional component as much as possible. Scalable universal copper-based packaging (CopperPak) service system, including miniature copper-based packaging (TyniCopk) and large-scale copper-based packaging (MassyCopk) modules, used to package discrete circuit components, not only solve the discrete circuit components size, heat transfer and positioning alignment issues, and simplify the packaging process and improve yield rate.

Imaging-based optical barcoding for relative humidity sensing based on meta-tip

In a wide range of applications such as healthcare treatment, environmental monitoring, food processing and storage, and semiconductor chip manufacturing, relative humidity (RH) sensing is required. However, traditional fiber-optic humidity sensors face the challenges of miniaturization and indirectly obtaining humidity values. Here, we propose and demonstrate an optical barcode technique by cooperating with RH meta-tip, which can predict the humidity values directly. Such RH meta-tip is composed of fiber-optic sensor based on surface plasmon resonance (SPR) effect and graphene oxide film as humidity sensitizer. While SPR sensor is composed of multimode fiber (MMF) integrated with metallic metasurface. Dynamic time warping (DTW) algorithm is used to obtain the warp path distance (WPD) sequence between the measured reflection spectrum and the spectra of the precalibrated database. The distance sequence is transformed into a pseudo-color barcode, and the humidity value is corresponded to the lowest distance, which can be read by human eyes. The RH measurement depends on the collective changes of the reflection spectrum rather than tracking a single specific resonance peak/dip. This work can open up new doors to the development of a humidity sensor with direct RH recognition by human eyes.

Chip Recombination Method in Planar Deprocessing – A Solution for Failure Analysis on Chip Edge Defects

Planar deprocessing is a vital failure analysis (FA) technique for semiconductor chip reverse engineering. The basic concept of planar deprocessing is to remove all the “unnecessary” materials of a chip to expose an area of interest (AOI) and maintain the chip planarity and surface evenness. Finger deprocessing is one of the common techniques applied to this concept. This technique is essential in physical FA, especially for advanced bulk fin field-effect transistor (FinFET) devices. The success of finger deprocessing technique depends on certain factors, one of which is the location of AOI region. Application of finger deprocessing becomes incredibly challenging for AOI close to chip edge due to the chip edge effect, i. e. the chip edge is deprocessed much faster than the chip center. Plasma focused ion beam (PFIB) planar deprocessing is the primary solution to solve this problem. However, the PFIB capability is a luxury tool for most analysis labs. To overcome this challenge, a novel chip recombination method is introduced. With this method, planar deprocess can be achieved by conventional finger deprocessing technique and more importantly can be applied in general analysis labs. This paper will discuss the newly developed method in a step-by-step guide basis and show two cases with AOI(s) in the chip edge region to demonstrate its capability.

High-accuracy quantitative principle of a new compact digital PCR equipment: Lab On An Array

Digital PCR (dPCR) is the third-generation PCR that enables real-time absolute quantification without reference materials. Recently, global diagnosis companies have developed new dPCR equipment. In line with the development, the Lab On An Array (LOAA) dPCR analyzer (Optolane) was launched last year. The LOAA dPCR is a semiconductor chip-based separation PCR type equipment. The LOAA dPCR includes Micro Electro Mechanical System that can be injected by partitioning the target gene into 56 to 20,000 wells. The amount of target gene per wells is digitized to 0 or 1 as the number of well gradually increases to 20,000 wells because its principle follows Poisson distribution, which allows the LOAA dPCR to perform precise absolute quantification. LOAA determined region of interest first prior to dPCR operation. To exclude invalid wells for the quantification, the LOAA dPCR has applied various filtering methods using brightness, slope, baseline, and noise filters. As the coronavirus disease 2019 has now spread around the world, needs for diagnostic equipment of point of care testing (POCT) are increasing. The LOAA dPCR is expected to be suitable for POCT diagnosis due to its compact size and high accuracy. Here, we describe the quantitative principle of the LOAA dPCR and suggest that it can be applied to various fields.

The Specter of Digital Rights

In the article, the author examines the problem of the impact of technological changes on the legal regulation of public relations, namely the development of digital technologies, how significant such an impact turned out to be and whether, in this regard, significant changes in the principles and mechanisms of legal regulation are required. It is asserted in the article that the problem how to adapt existing legal forms in order to address inevitable changes in public relationships (does not matter what the cause of these changes is: the so called “digitalization” or something else) may be relatively easily resolved. What we need to do is to segregate those aspects of the factual side of relationships in question that should have legal consequences from the rest, that is from those aspects that may be ignored by law. In order to illustrate this thesis the author considers two examples: the semiconductor chip protection and the electronic signature as a way to identify an entity who expressed a will. The author comes to the conclusion that the existing legal instruments for regulating the emerging new factual relations are sufficient, but they must be used correctly. The author gives examples of such law enforcement within the framework of the article.

Semiconductor Chip Electrical Interconnection and Bonding by Nano-Locking with Ultra-Fine Bond-Line Thickness

The potential of an innovation for establishing a simultaneous mechanical, thermal, and electrical connection between two metallic surfaces without requiring a prior time-consuming and expensive surface nanoscopic planarization and without requiring any intermediate conductive material has been explored. The method takes advantage of the intrinsic nanoscopic surface roughness on the interconnecting surfaces: the two surfaces are locked together for electrical interconnection and bonding with a conventional die bonder, and the connection is stabilized by a dielectric adhesive filled into nanoscale valleys on the interconnecting surfaces. This “nano-locking” (NL) method for chip interconnection and bonding is demonstrated by its application for the attachment of high-power GaN-based semiconductor dies to its device substrate. The bond-line thickness of the present NL method achieved is under 100 nm and several hundred times thinner than those achieved using mainstream bonding methods, resulting in a lower overall device thermal resistance and reduced electrical resistance, and thus an improved overall device performance and reliability. Different bond-line thickness strongly influences the overall contact area between the bonding surfaces, and in turn results in different contact resistance of the packaged devices enabled by the NL method and therefore changes the device performance and reliability. The present work opens a new direction for scalable, reliable, and simple nanoscale off-chip electrical interconnection and bonding for nano- and micro-electrical devices. Besides, the present method applies to the bonding of any surfaces with intrinsic or engineered surface nanoscopic structures as well.

Green Nanofabrication Opportunities in the Semiconductor Industry: A Life Cycle Perspective

The turn of the 21st century heralded in the semiconductor age alongside the Anthropocene epoch, characterised by the ever-increasing human impact on the environment. The ecological consequences of semiconductor chip manufacturing are the most predominant within the electronics industry. This is due to current reliance upon large amounts of solvents, acids and gases that have numerous toxicological impacts. Management and assessment of hazardous chemicals is complicated by trade secrets and continual rapid change in the electronic manufacturing process. Of the many subprocesses involved in chip manufacturing, lithographic processes are of particular concern. Current developments in bottom-up lithography, such as directed self-assembly (DSA) of block copolymers (BCPs), are being considered as a next-generation technology for semiconductor chip production. These nanofabrication techniques present a novel opportunity for improving the sustainability of lithography by reducing the number of processing steps, energy and chemical waste products involved. At present, to the extent of our knowledge, there is no published life cycle assessment (LCA) evaluating the environmental impact of new bottom-up lithography versus conventional lithographic techniques. Quantification of this impact is central to verifying whether these new nanofabrication routes can replace conventional deposition techniques in industry as a more environmentally friendly option.