Failure Analysis of Embedded Non-Volatile Memory with Nano- and Micro-Probing Techniques

2015 ◽  
Author(s):  
Xiang-Dong Wang ◽  
Arnold Yazzie ◽  
John Buchert ◽  
Laurel Will ◽  
Ping Wang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Physical Analysis ◽  
Semiconductor Chip ◽  
Atomic Force ◽  
First Case ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
Almost All ◽  
Individual Column

Abstract Embedded non-volatile memory (NVM) technologies are used in almost all areas of semiconductor chip applications, as it becomes increasingly vital to retain information when the electronics power is off. Nano-probing techniques, such as atomic force probe (AFP), allow us to access individual devices at contact or via levels and characterize the details as much as possible before a decision can be made for physical analysis. This paper reports the application of AFP to characterize each individual bit at contact level or individual column at via1 level. It presents two cases to identify the failures encountered in fabricated embedded NVM: column-column leakage and single bit erase failure. The first case shows that silicide residual could cause column to column leakage by creating electrical path between active areas of adjacent columns, while the second case shows that single bit failures due to low erase current can be recovered with repeated program/erase cycle.

scholarly journals Resolution of Customer Return Non-Volatile Memory Data Retention Bit Failures through Bit Map Verification and Bit Cell Characterization by Nanoprobe Analysis

2021 ◽  
Author(s):  
Randal Mulder
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Nonvolatile Memory ◽  
Physical Analysis ◽  
Data Retention ◽  
Tem Analysis ◽  
Cell Characterization ◽  
Atomic Force ◽  
Programming Error ◽  
Non Volatile Memory

Abstract A major customer had been returning devices for nonvolatile memory (NVM) data retention bit failures. The ppm level was low but the continued fallout at the customer location was causing a quality and reliability concern. The customer wanted a resolution as to the cause of the failures and for a corrective action. An NVM bit data retention failure occurs when a programmed bit loses it programmed data state over time and flips to the opposite data state (0 -> 1 or 1 -> 0) causing a programming error. Previous failure analysis results on several failing devices with a single NVM bit data retention failure was inconclusive. TEM analysis showed no difference between the failing bit and neighboring passing bit. The lack of results led to the questioning of the accuracy of the bit map documentation and if the TEM analysis was being performed at the correct bit location. Bit map documentation takes the failing bit's electrical address and converts it to a physical address location. If the bit map documentation is incorrect, locating the failing bit is not possible and physical failure analysis will not be performed at the correct bit location. This paper will demonstrate how Atomic Force Probe (AFP) nanoprobe analysis was used to first verify the bit map documentation by determining the programming of bits at specific locations through bit cell characterization; and then characterize the failing bit location to verify the programming error and determine the possible failure mechanism based on its electrical signature followed by the appropriate physical analysis to determine the failure mechanism.

The Electrical Characterization and Physical Failure Analysis for Transistor Gate Leakage

2006 ◽  
Author(s):  
Tsung-Te Li ◽  
Chao-Chi Wu ◽  
Jung-Hsiang Chuang ◽  
Jon C. Lee
Keyword(s):  
Failure Analysis ◽  
Electrical Characterization ◽  
Physical Analysis ◽  
Gate Leakage ◽  
Force Microscopy ◽  
Atomic Force ◽  
Transmission Electron ◽  
Voltage Stress ◽  
Leakage Site

Abstract This article describes the electrical and physical analysis of gate leakage in nanometer transistors using conducting atomic force microscopy (C-AFM), nano-probing, transmission electron microscopy (TEM), and chemical decoration on simulated overstressed devices. A failure analysis case study involving a soft single bit failure is detailed. Following the nano-probing analysis, TEM cross sectioning of this failing device was performed. A voltage bias was applied to exaggerate the gate leakage site. Following this deliberate voltage overstress, a solution of boiling 10%wt KOH was used to etch decorate the gate leakage site followed by SEM inspection. Different transistor leakage behaviors can be identified with nano-probing measurements and then compared with simulation data for increased confidence in the failure analysis result. Nano-probing can be used to apply voltage stress on a transistor or a leakage path to worsen the weak point and then observe the leakage site easier.

Application of AFP in Resolving Systematic Issue in Wafer Fabrication

2013 ◽  
Author(s):  
Hui Peng Ng ◽  
Ghim Boon Ang ◽  
Chang Qing Chen ◽  
Alfred Quah ◽  
Angela Teo ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Failure Mechanisms ◽  
Critical Role ◽  
Electrical Characterization ◽  
Process Technology ◽  
Atomic Force ◽  
Defect Localization ◽  
Non Volatile Memory ◽  
Visual Failure

Abstract With the evolution of advanced process technology, failure analysis is becoming much more challenging and difficult particularly with an increase in more erratic defect types arising from non-visual failure mechanisms. Conventional FA techniques work well in failure analysis on defectively related issue. However, for soft defect localization such as S/D leakage or short due to design related, it may not be simple to identify it. AFP and its applications have been successfully engaged to overcome such shortcoming, In this paper, two case studies on systematic issues due to soft failures were discussed to illustrate the AFP critical role in current failure analysis field on these areas. In other words, these two case studies will demonstrate how Atomic Force Probing combined with Scanning Capacitance Microscopy were used to characterize failing transistors in non-volatile memory, identify possible failure mechanisms and enable device/ process engineers to make adjustment on process based on the electrical characterization result. [1]

Providing Security of Vital Data for Conventional Microcontroller Applications

2015 ◽  
Vol 789-790 ◽  
pp. 1059-1066
Author(s):  
Bayram Akdemir ◽  
Hasan Üzülmez
Keyword(s):  
Real Time ◽  
Power Loss ◽  
Gray Code ◽  
The Other ◽  
Reading Problem ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
High Flexibility ◽  
Almost All

Microcontrollers are widely used in industrial world, and almost all kind of devices were based on microcontroller to achieve high flexibility and abilities. All microcontrollers have nonvolatile and volatile memories to execute the software. During the running, microcontroller calculates many variables and records them to any non-volatile memory to use later. After re-energizing, microcontroller takes the data calculated before the power off and executes the program. In case of any electrical writing error or any power loss during the writing procedure, un-written memory blocks or any un-written data leads to malfunctions. Proposed method uses a gray code based signed two memory blocks to secure the memory reserved for data. Microcontroller uses these memory blocks in alternately. Even if microcontroller has no any real-time ability, gray code provides a guarantee which block is written in last. For every re-starting microcontroller dos not lose the data. In case of any reading problem during the starting, microcontroller has two chances to decide the action. One is to start with default values and the other is to start with the previous data. This study is tested at elevator applications not to lose position and vital values.

Application of Nanoprobing on Subtle Defects in the Embedded Non-Volatile Memory Device

2019 ◽  
Author(s):  
C. Q. Chen ◽  
P. T. Ng ◽  
S. P. Neo ◽  
P. K. Tan ◽  
A. C. T. Quah ◽  
...  
Keyword(s):  
Semiconductor Devices ◽  
Direct Analysis ◽  
Memory Device ◽  
Charge Storage ◽  
Physical Analysis ◽  
Electron Charge ◽  
Data Memory ◽  
Key Word ◽  
Non Volatile Memory ◽  
Volatile Memory

Abstract Non-volatile memory is the most important memory device in IC chips. As a memory, embedded non-volatile memory (NVM) is a fundamental structure in many kinds of semiconductor devices. It is commonly used in the modern electrical appliance as a code or data memory. For different applications, there are different memory designs or IP, like ROM, OTP, Flash, MRAM, PCRAM etc. The physical mechanism of these NVMs are different, some are electron based, some are resistance based and fuse or anti-fused based. The experiment described in this paper is performed on an electron charge storage based NVM. That means a medium is employed to store electron charge to differentiate two statuses “0” and “1”. Floating Poly gate is this medium used as electron charge storage in this NVM. Since the storage medium is in floating condition, it cannot be accessed externally. The methods of performing direct analysis are limited for this kind of device, especially in the case of subtle defects or soft fail. As semiconductor devices scale, the defects become smaller and more subtle. Nanoprobing is usually the only way to find the defect location electrically before any further physical analysis. In this experiment, the single bit NVM fail was analyzed. Different PFA methods used during the analysis, failed to find the defect. Nanoprobing was employed to precisely isolate the defect. Key word: nanoprobing, NVM, subtle defect, Poly-crystalline, floating gate

Test and Failure Analysis Implications of a Novel Inter-Bit Dependency in a Non-Volatile Memory

1997 ◽  
Author(s):  
D. Boyne ◽  
J. Goertz ◽  
D. Parsons
Keyword(s):  
Failure Analysis ◽  
Automated Testing ◽  
Test Time ◽  
Checkerboard Pattern ◽  
Nonvolatile Memories ◽  
Non Volatile Memory ◽  
History Of ◽  
Volatile Memory ◽  
Field Oxide

Abstract Failure analysis of non-volatile memory arrays can be complicated by the history of bits elsewhere in the array. This generally is in contrast to volatile memories, in which the state of all bits can quickly be reset by over-writing the bits, or by simply removing power from the array. On one of our products, EEPROM bits failed to program if certain patterns of bits were programmed elsewhere in the EEPROM array. During programming, high voltages (>18 volts) are present within the EEPROM array. Such voltage levels caused a narrow field oxide region to break down, thereby pulling down the programming voltage and preventing the successful programming of EEPROM transistors. What complicated the analysis, however, was that the breakdown only occurs if a checkerboard pattern is being programmed in one part of the array, while specific other EEPROM bits had previously been programmed elsewhere in the array. Until the failure mechanism was well understood, electrical screens were difficult to implement, because they typically do not account for complicated interactions between bits. This is especially true for nonvolatile memories, for which test time costs often prohibit the use of complicated test patterns with improved test coverage. This paper reviews the failure analysis, and proceeds to highlight the importance of knowing the contents of nonvolatile arrays prior to performing either failure analysis or automated testing on such an array. The case study therefore applies to both test and failure analysis engineers.

scholarly journals On Ciphers that Continuously Access the Non-Volatile Key

2017 ◽  
pp. 52-79 ◽  
Author(s):  
Vasily Mikhalev ◽  
Frederik Armknecht ◽  
Christian Müller
Keyword(s):  
Point Of View ◽  
Limited Area ◽  
Practical Point ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
Encryption Decryption ◽  
The One ◽  
Almost All ◽  
The Impact ◽  
Memory Techniques

Due to the increased use of devices with restricted resources such as limited area size, power or energy, the community has developed various techniques for designing lightweight ciphers. One approach that is increasingly discussed is to use the cipher key that is stored on the device in non-volatile memory not only for the initialization of the registers but during the encryption/decryption process as well. Recent examples are the ciphers Midori (Asiacrypt’15) and Sprout (FSE’15). This may on the one hand help to save resources, but also may allow for a stronger key involvement and hence higher security. However, only little is publicly known so far if and to what extent this approach is indeed practical. Thus, cryptographers without strong engineering background face the problem that they cannot evaluate whether certain designs are reasonable (from a practical point of view) which hinders the development of new designs.In this work, we investigate this design principle from a practical point of view. After a discussion on reasonable approaches for storing a key in non-volatile memory, motivated by several commercial products we focus on the case that the key is stored in EEPROM. Here, we highlight existing constraints and derive that some designs, based on the impact on their throughput, are better suited for the approach of continuously reading the key from all types of non-volatile memory. Based on these findings, we improve the design of Sprout for proposing a new lightweight stream cipher that (i) has a significantly smaller area size than almost all other stream ciphers and (ii) can be efficiently realized using common non-volatile memory techniques. Hence, we see our work as an important step towards putting such designs on a more solid ground and to initiate further discussions on realistic designs.

Diamond Probe Applications for Nanoprobing

2016 ◽  
Author(s):  
Sweta Pendyala ◽  
Andrew Dalton ◽  
Sean Zumwalt ◽  
John Miller
Keyword(s):  
Failure Analysis ◽  
Semiconductor Devices ◽  
The Other ◽  
Physical Analysis ◽  
Atomic Force ◽  
Scale Down ◽  
Diamond Probe

Abstract As technology continues to scale down, semiconductor devices and circuitry have become more complex. The layouts are more integrated and the devices do not isolate at contact level like they used to. Due to this, nanoprobing cannot always localize the defect to one gate finger and as a result the follow-on physical analysis gets more complicated and time consuming. In this paper, we will explore an approach to simplify a given circuit and localize the failing finger in that circuit by cutting metal lines using diamond nano-probes [1] on the FEI Hyperion Atomic Force Probe (AFP) Platform. We will also describe some of the other applications of diamond nano-probes in facilitating semiconductor failure analysis.

Latent Flash Single Bit and Multiple Bits Systematic Approach to Failure Analysis

2008 ◽  
Author(s):  
Hoang-Yen To ◽  
Dat Nguyen ◽  
Clyde Dunn ◽  
Detric Davis
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Systematic Approach ◽  
Failure Modes ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Electrical Failure ◽  
Non Volatile Memory ◽  
Different Temperatures ◽  
Volatile Memory

Abstract The flash considered for failure analysis in this paper is a non volatile memory with a NOR architecture in the array and a stacked gate for the bit cell. The flash failure was from data gain reported from various stages and at different temperatures after leaving the wafer fabrication. The failure can be single bit failure (SBF) or multiple bit failure (MBF). The FA process is comprised of two steps termed electrical failure analysis (EFA) and physical failure analysis (PFA). This paper discusses the method to differentiate failure modes and the efforts of fault isolation. Micro probing and nano probe characterization were important in the understanding of the failure mechanism. As seen in the EFA/PFA section, the reported SBF/MBF failures were actually due to a defect in the Mux and not at the bit cell.

ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory

2015 ◽  
Vol E98.A (12) ◽  
pp. 2494-2504 ◽  
Author(s):  
Masashi TAWADA ◽  
Shinji KIMURA ◽  
Masao YANAGISAWA ◽  
Nozomu TOGAWA
Keyword(s):  
Code Generation ◽  
Non Volatile Memory ◽  
Volatile Memory
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