Case Study and Fault Modeling for Wrong Redundancy Evaluation on DRAM Devices
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Abstract The characterization of failure modes of DRAM is often straight forward if array related hard failures with specific addresses for localization are concerned. The paper presents a case study of a bitline oriented failure mode connected to a redundancy evaluation in the DRAM periphery. The failure mode analysis and fault modeling focus both on the root-cause and on the test aspects of the problem.
2015 ◽
Vol 727-728
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pp. 637-640
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2018 ◽
Vol 29
(15)
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pp. 1225-1237
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2007 ◽
Vol 340-341
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pp. 1393-1398
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2020 ◽
Vol ahead-of-print
(ahead-of-print)
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