Commonality Analysis for Multiple Chain Integrity Failures

Mapping Intimacies ◽

10.31399/asm.cp.istfa2021p0334 ◽

2021 ◽

Author(s):

Angelo Antonio Merassi ◽

Matteo Medda

Keyword(s):

Physical Analysis ◽

Layout Analysis ◽

Commonality Analysis ◽

Emission Microscopy ◽

Scan Chain ◽

Multiple Chain ◽

Complex Cases

Abstract The aim of this paper is to disclose an alternative FA approach to handle complex cases, showing multiple chain failures with multiple candidates. Starting from a commonality layout analysis of candidates resulting from the diagnosis, it is possible to identify a common interconnection shared between the several candidates, already at schematic level. The effectiveness of such analysis has been successfully verified by means of a photo-emission microscopy (PEM) analysis, while running scan chain patterns and by physical analysis.

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Yield and Failure Analysis of FinFET Source to Drain Leakage in 12nm Technology

ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2020p0038 ◽

2020 ◽

Author(s):

Felix Beaudoin ◽

Satish Kodali ◽

Rohan Deshpande ◽

Wayne Zhao ◽

Edmund Banghart ◽

...

Keyword(s):

Failure Analysis ◽

Fault Localization ◽

Detailed Characterization ◽

Laser Stimulation ◽

Emission Microscopy ◽

Scan Chain ◽

Multiple Samples ◽

Tem Lamella ◽

Diffusion Activation

Abstract Fault localization using both dynamic laser stimulation and emission microscopy was used to localize the failing transistors within the failing scan chain latch on multiple samples. Nanoprobing was then performed and the source to drain leakage in N-type FinFETs was identified. After extensive detailed characterization, it was concluded that the N-type dopant signal was likely due to projections from the source/drain regions included in the TEM lamella. Datamining identified the scan chain fail to be occurring uniquely for a specific family of tools used during source/drain implant diffusion activation. This paper discusses the processes involved in yield delta datamining of FinFET and its advantages over failure characterization, fault localization, nanoprobing, and physical failure analysis.

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Analog and Mixed Signal Diagnosis Flow Using Fault Isolation Techniques and Simulation

ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2020p0091 ◽

2020 ◽

Author(s):

Tommaso Melis ◽

Emmanuel Simeu ◽

Etienne Auvray

Keyword(s):

Failure Analysis ◽

Fault Simulation ◽

Fault Isolation ◽

Physical Analysis ◽

Actual Process ◽

Electrical Test ◽

Simulation Tools ◽

Isolation Techniques ◽

Process Node ◽

Emission Microscopy

Abstract Getting accurate fault isolation during failure analysis is mandatory for success of Physical Failure Analysis (PFA) in critical applications. Unfortunately, achieving such accuracy is becoming more and more difficult with today’s diagnosis tools and actual process node such as BCD9 and FinFET 7 nm, compromising the success of subsequent PFA done on defective SoCs. Electrical simulation is used to reproduce emission microscopy, in our previous work and, in this paper, we demonstrate the possibility of using fault simulation tools with the results of electrical test and fault isolation techniques to provide diagnosis with accurate candidates for physical analysis. The experimental results of the presented flow, from several cases of application, show the validity of this approach.

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Advanced Fault Localization through the Use of Tester Based Diagnostics with LVI, LVP, CPA, and PEM

ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2013p0313 ◽

2013 ◽

Author(s):

Laura Safran ◽

John Sylvestri ◽

Dave Albert ◽

Zhigang Song ◽

Patrick McGinnis

Keyword(s):

Technology Development ◽

Photon Emission ◽

Fault Localization ◽

Parameter Analysis ◽

Advanced Technology ◽

Tem Analysis ◽

Voltage Imaging ◽

First Case ◽

Emission Microscopy ◽

Scan Chain

Abstract Fault localization on functional macros during advanced technology development requires a complex combination of tester based diagnostics and image based techniques including laser voltage imaging (LVI), laser voltage probing (LVP), critical parameter analysis (CPA) with laser stimulation and photon emission microscopy (PEM). These techniques are exemplified in the following three case studies. The first case involves a voltage sensitive SRAM block fail which was localized to a resistive via through the use of CPA, LVI and LVP. The second case demonstrates how a hard fail (a net-to-net metal short) in a scan chain was localized through use of tester based diagnostics, LVI, LVP and PEM. Finally, the last case shows how a condition sensitive failing latch chain was localized through CPA, LVI, LVP and PEM. Subsequent atomic force probing (AFP) identified source-drain leakage in one of the localized devices, and TEM analysis revealed a dislocation in the failing FET. Each of these cases demonstrates the value in utilizing tester based diagnostics along with laser based imaging and photon emission microscopy to localize failures.

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