Net-Shape-Based Automated Detection of Integrated-Circuit Layout Plagiarism

Plagiarism of integrated-circuit (IC) layout is a problem encountered both in academia and in industry. A procedure was proposed that compares IC layouts based on the physical representation of particular electrical nets, i.e., on the shape of the features drawn on conducting layers (metals and polysilicon). At the heart of this method is the Needleman–Wunsch algorithm, used for decades in tools aligning sequences of amino acids or nucleotides. Here, it is used to quantify the visual similarity of nets within the pair of layouts being compared. The method was implemented in Python and successfully used to identify clusters of similar layouts within two pools of designs: one composed of logic gates and one containing operational transconductance amplifiers.

Design and Synthesis of a MOD 13 Binary Down Counter

This work explains the process of designing and synthesizing a MOD 13 binary down counter using 180 nm CMOS technology transistors. The beginning of the count is a combination of 1110(2), the end of the count is 0010(2). Simulations are made at the circuit level (transient analysis) to verify that the circuit functions correctly, then the integrated circuit layout is prepared by connecting the components manually. Finally, the layout is simulated to see how the existence of parasitic resistances and capacitances affect the output signals and it is used to estimate the maximum allowable clock frequency (fclk).

Design and Synthesis of a MOD 13 Binary Down Counter

This work explains the process of designing and synthesizing a MOD 13 binary down counter using 180 nm CMOS technology transistors. The beginning of the count is a combination of 1110(2), the end of the count is 0010(2). Simulations are made at the circuit level (transient analysis) to verify that the circuit functions correctly, then the integrated circuit layout is prepared by connecting the components manually. Finally, the layout is simulated to see how the existence of parasitic resistances and capacitances affect the output signals and it is used to estimate the maximum allowable clock frequency (fclk).

Dimensional Expressivity Analysis of Parametric Quantum Circuits

Parametric quantum circuits play a crucial role in the performance of many variational quantum algorithms. To successfully implement such algorithms, one must design efficient quantum circuits that sufficiently approximate the solution space while maintaining a low parameter count and circuit depth. In this paper, develop a method to analyze the dimensional expressivity of parametric quantum circuits. Our technique allows for identifying superfluous parameters in the circuit layout and for obtaining a maximally expressive ansatz with a minimum number of parameters. Using a hybrid quantum-classical approach, we show how to efficiently implement the expressivity analysis using quantum hardware, and we provide a proof of principle demonstration of this procedure on IBM's quantum hardware. We also discuss the effect of symmetries and demonstrate how to incorporate or remove symmetries from the parametrized ansatz.

Fracture Strength Characterization of the Die Active Side and Back Side for a Realistic Die Crack Assessment

This paper discusses the characterization of an integrated circuit (IC) silicon die fracture strength to have a realistic die crack assessment. The evaluation was conducted using a 3-point bend test setup to measure the die strength of actual IC dies. Both the active side and the back side of the IC die were tested for 2 types of dies with different active side circuit layout. Results showed that the difference in the die active side circuit layout or structure has impact on die strength. It was also found that the active side was weaker than the back side. This implies that both the active side and the back side of an actual IC die must be subjected to fracture strength characterization to have an assessment that would be in a better agreement with real condition. Using only the strength of the back side would result in over-estimating the die strength. The common approach of using the fracture strength of the die back side to characterize the die strength is not realistic and can mislead the assessment of die crack or semiconductor package robustness.