scholarly journals WINTER CONCRETING PROCESS DESIGN IMPROVEMENT IN MODERN CONSTRUCTION

Author(s):  
E. Dugersuren ◽  
M. M. Titov
Author(s):  
Rennier S. Rodriguez ◽  
Frederick Ray I. Gomez

The paper focused on the elimination of die crack occurrence at the diebond process. Design of experiment (DOE) was done on the pick and place rubber-tip design and an improved design was finalized. The improved rubber-tip configuration with smaller vacuum design and full contact surface eventually resolved the die crack issues, improving the manufacturability of thin silicon die during diebond process. For future works, the configuration could be applied for packages with similar requirement.


Author(s):  
D.Yu. Serikov ◽  
◽  
V.Yu. Bliznyukov ◽  
Yu.N. Pilnik ◽  

2020 ◽  
Vol 40 (6) ◽  
pp. 488-490
Author(s):  
S. Yu. Kalyakulin ◽  
V. V. Kuz’min ◽  
E. V. Mitin ◽  
S. P. Sul’din

Author(s):  
Marie-Pascale Chagny ◽  
John A. Naoum

Abstract Over the years, failures induced by an electrostatic discharge (ESD) have become a major concern for semiconductor manufacturers and electronic equipment makers. The ESD events that cause destructive failures have been studied extensively [1, 2]. However, not all ESD events cause permanent damage. Some events lead to recoverable failures that disrupt system functionality only temporarily (e.g. reboot, lockup, and loss of data). These recoverable failures are not as well understood as the ones causing permanent damage and tend to be ignored in the ESD literature [3, 4]. This paper analyzes and characterizes how these recoverable failures affect computer systems. An experimental methodology is developed to characterize the sensitivity of motherboards to ESD by simulating the systemlevel ESD events induced by computer users. The manuscript presents a case study where this methodology was used to evaluate the robustness of desktop computers to ESD. The method helped isolate several weak nets contributing to the failures and identified a design improvement. The result was that the robustness of the systems improved by a factor of 2.


Author(s):  
Hung-Sung Lin ◽  
Ying-Chin Hou ◽  
Juimei Fu ◽  
Mong-Sheng Wu ◽  
Vincent Huang ◽  
...  

Abstract The difficulties in identifying the precise defect location and real leakage path is increasing as the integrated circuit design and process have become more and more complicated in nano scale technology node. Most of the defects causing chip leakage are detectable with only one of the FA (Failure Analysis) tools such as LCD (Liquid Crystal Detection) or PEM (Photon Emission Microscope). However, due to marginality of process-design interaction some defects are often not detectable with only one FA tool [1][2]. This paper present an example of an abnormal power consumption process-design interaction related defect which could only be detected with more advanced FA tools.


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