scholarly journals AN APPROACH OF UBIQUITOUS DEVICES USING T-ENGINE IN VIETNAM

2011 ◽  
Vol 14 (4) ◽  
pp. 16-23
Author(s):  
Hung Hoa Nguyen ◽  
Huy Quang Nguyen ◽  
Vu Duc Anh Dinh
Keyword(s):  
Embedded Systems ◽  
Real Time ◽  
Control Mechanism ◽  
Time Constraints ◽  
Development Platform ◽  
Wide Range ◽  
Different Types ◽  
Hardware Platforms ◽  
Automatic Systems ◽  
Additional Hardware

The 21st century is the era of Ubiquitous Computing where computing devices are present everywhere in our lives. To satisfy the development of this tendency, many hardware platforms have been proposed for developing Ubiquitous devices. Among them, T-Engine, an open standardized development platform for embedded systems, is one of the most popular platforrms. It is nowadays compatible with embedded equipments for a wide range of fields. In Vietnam, T-Engine has just been introduced for 4 years. However, most of the ubiquitous applications using T-Engine are developed restrictively based on the standard hardware of T-Engine. One issue that arises is the necessity of a solution to expand T-Engine hardware and use it to control automatic systems to satisfy different types of Ubiquitous devices. This research is to propose an approach to use T-Engine in the Ubiquitous Devices that require the attachment of the additional hardware as well as the complicated control mechanism with real time constraints. In this research, we proposed an expanding solution T-Engine through the extension bus. Besides that, we consider the timing problems in bus transaction and problems in real-time programming. A simple robot demonstration has also been designed and implemented to prove the feasibility of our model. This approach will open up a new tendency of developing complicated Ubiquitous devices using T-Engine in Vietnam.

scholarly journals A Novel Rail-Network Hardware Simulator for Embedded System Programming

Electronics ◽  
2020 ◽  
Vol 10 (1) ◽  
pp. 13
Author(s):  
Balaji M ◽  
Chandrasekaran M ◽  
Vaithiyanathan Dhandapani
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
Real Time ◽  
Learning Outcomes ◽  
Real World ◽  
Time Constraints ◽  
Network Simulator ◽  
Practical Applications ◽  
Rail Network ◽  
Knowledge Enhancement

A Novel Rail-Network Hardware with simulation facilities is presented in this paper. The hardware is designed to facilitate the learning of application-oriented, logical, real-time programming in an embedded system environment. The platform enables the creation of multiple unique programming scenarios with variability in complexity without any hardware changes. Prior experimental hardware comes with static programming facilities that focus the students’ learning on hardware features and programming basics, leaving them ill-equipped to take up practical applications with more real-time constraints. This hardware complements and completes their learning to help them program real-world embedded systems. The hardware uses LEDs to simulate the movement of trains in a network. The network has train stations, intersections and parking slots where the train movements can be controlled by using a 16-bit Renesas RL78/G13 microcontroller. Additionally, simulating facilities are provided to enable the students to navigate the trains by manual controls using switches and indicators. This helps them get an easy understanding of train navigation functions before taking up programming. The students start with simple tasks and gradually progress to more complicated ones with real-time constraints, on their own. During training, students’ learning outcomes are evaluated by obtaining their feedback and conducting a test at the end to measure their knowledge acquisition during the training. Students’ Knowledge Enhancement Index is originated to measure the knowledge acquired by the students. It is observed that 87% of students have successfully enhanced their knowledge undergoing training with this rail-network simulator.

JPEG Image Decoding and Display System Design Based on ZedBoard Development Platform

2014 ◽  
Vol 513-517 ◽  
pp. 2476-2479 ◽  
Author(s):  
Qiong Wu ◽  
Yao Tian Zhang ◽  
Jun Wang
Keyword(s):  
High Resolution ◽  
Real Time ◽  
Design Flow ◽  
Stream Data ◽  
Development Environment ◽  
Data Movement ◽  
Jpeg Image ◽  
Development Platform ◽  
Wide Range ◽  
Image Decoding

JPEG decoding algorithm has become an international mainstream image compression standard, because of its wide range of applications, easy implementation, supporting for lossless compression and other characteristics [. This thesis is to explain how to design a high-resolution JPEG image decoding system architecture, which supports for real-time display and has good scalability as well. We choosing newly developed ZedBoard development board of Xilinx corporation as development platform and EDK (Embedded Development Kit) as development environment [. The design flow is to read JPEG stream data stored in DDR and store the decoding data in DDR after finishing the hardware decoding. Finally we use VDMA to translate the stream in order to display on a monitor connected to the HDMI interface. In this system, we adopt AXI bus with a hierarchical technology to achieve IP interconnection, adopt hardware decoding to achieve high-resolution image decoding and adopt VDMA hardware data movement to achieve real-time display based on ARM Cortex A9 dual-core processor software design.

scholarly journals SAGE: A S plit- A rchitecture Methodolo g y for E fficient End-to-End Autonomous Vehicle Control

2021 ◽  
Vol 20 (5s) ◽  
pp. 1-22
Author(s):  
Arnav Malawade ◽  
Mohanad Odema ◽  
Sebastien Lajeunesse-degroot ◽  
Mohammad Abdullah Al Faruque
Keyword(s):  
High Resolution ◽  
Real Time ◽  
Autonomous Vehicles ◽  
Autonomous Vehicle ◽  
Industry Standard ◽  
Wide Range ◽  
Energy Consuming ◽  
Time Latency ◽  
4G Lte ◽  
Hardware Platforms

Autonomous vehicles (AV) are expected to revolutionize transportation and improve road safety significantly. However, these benefits do not come without cost; AVs require large Deep-Learning (DL) models and powerful hardware platforms to operate reliably in real-time, requiring between several hundred watts to one kilowatt of power. This power consumption can dramatically reduce vehicles’ driving range and affect emissions. To address this problem, we propose SAGE: a methodology for selectively offloading the key energy-consuming modules of DL architectures to the cloud to optimize edge, energy usage while meeting real-time latency constraints. Furthermore, we leverage Head Network Distillation (HND) to introduce efficient bottlenecks within the DL architecture in order to minimize the network overhead costs of offloading with almost no degradation in the model’s performance. We evaluate SAGE using an Nvidia Jetson TX2 and an industry-standard Nvidia Drive PX2 as the AV edge, devices and demonstrate that our offloading strategy is practical for a wide range of DL models and internet connection bandwidths on 3G, 4G LTE, and WiFi technologies. Compared to edge-only computation, SAGE reduces energy consumption by an average of 36.13% , 47.07% , and 55.66% for an AV with one low-resolution camera, one high-resolution camera, and three high-resolution cameras, respectively. SAGE also reduces upload data size by up to 98.40% compared to direct camera offloading.

scholarly journals Open-Source FPGA Coprocessor for the Doppler Emulation of Moving Fluids

Micromachines ◽  
2021 ◽  
Vol 12 (12) ◽  
pp. 1549
Author(s):  
Stefano Ricci
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
Open Source ◽  
Real Time ◽  
Field Programmable Gate Array ◽  
Synthetic Signal ◽  
Doppler System ◽  
Wide Range ◽  
Field Programmable ◽  
Moving Fluid

Embedded systems are nowadays employed in a wide range of application, and their capability to implement calculation-intensive algorithms is growing quickly and constantly. This result is obtained by the exploitation of powerful embedded processors that are often connected to coprocessors optimized for a particular application. This work presents an open-source coprocessor dedicated to the real-time generation of a synthetic signal that mimics the echoes produced by a moving fluid when investigated by ultrasounds. The coprocessor is implemented in a Field Programmable Gate Array (FPGA) device and integrated in an embedded system. The system can replace the complex and inaccurate flow-rigs employed in laboratorial tests of Doppler ultrasound systems and methods. This paper details the coprocessor and its standard interfaces, and shows how it can be integrated in the wider architecture of an embedded system. Experiments showed its capability to emulate a fluid flowing in a pipe when investigated by an echographic Doppler system.

scholarly journals A Group-Based Energy-Efficient Dual Priority Scheduling for Real-Time Embedded Systems

Information ◽  
2020 ◽  
Vol 11 (4) ◽  
pp. 191
Author(s):  
Yongqi Ge ◽  
Rui Liu
Keyword(s):  
Energy Consumption ◽  
Embedded Systems ◽  
Real Time ◽  
System Reliability ◽  
Energy Efficient ◽  
Worst Case ◽  
Priority Scheduling ◽  
Different Types ◽  
Time Overhead ◽  
Case Response

As the limitation of energy consumption of real-time embedded systems becomes more and more strict, it has been difficult to ignore the time overhead and energy consumption of context switches for fixed-priority tasks with preemption scheduling (FPP) in multitasking environments. In addition, the scheduling for different types of tasks may disrupt each other and affect system reliability. A group-based energy-efficient dual priority scheduling (GEDP) is proposed in this paper. The GEDP isolates different types of tasks to avoid the disruption. Furthermore, it also reduces context switches effectively, thus decreasing system energy consumption. As many studies ignored the context switches’ overhead in the worst-case response time (WCRT) model, and it will affect the accuracy of WCRT, thereby affecting the system schedulability. Consequently, the WCRT model is improved based on considering context switches’ overhead. The GEDP is designed and implemented in Linux, and the time overhead and energy consumption of context switches is compared in different situations with GEDP and FPP. The experimental results show that GEDP can reduce context switches by about 1% and decrease energy consumption by about 0.6% for given tasks.

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