scholarly journals Low-Power Low-Area architecture of Probability Density Function Estimation for Histogram Equalization

Author(s):  
Koteswar Rao Bonagiri ◽  
Giri Babu Kande ◽  
P. Chandrasekhar Reddy

Estimation of Probability Density Functions (PDFs) in view of accessible information is critical issue emerging in various fields, for example, broadcast communications, machine learning, information mining, design pattern recognition and Personal Computer (PC) vision. In this paper, the Look-Up Table–Carry Select Adder-PDF (LUT-CSLA-PDF) mehod is implemented to increase system performance. The LUT is one of the fast way to recognize a complex function in the digital logic circuit. In this work, The FPGA (field programmable gate array) analysis, LUT, slices, flip flops, frequency are improved as well as ASIC (application specified integrated chip) implementation analysis an area, power, delay, Area Power Product (APP), Area Delay Product (ADP) are enhanced in LUT-CSLA-PDF technique compared to conventional methods.

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 2023
Author(s):  
Thanikodi Manoj Kumar ◽  
Kasarla Satish Reddy ◽  
Stefano Rinaldi ◽  
Bidare Divakarachari Parameshachari ◽  
Kavitha Arunachalam

Nowadays, a huge amount of digital data is frequently changed among different embedded devices over wireless communication technologies. Data security is considered an important parameter for avoiding information loss and preventing cyber-crimes. This research article details the low power high-speed hardware architectures for the efficient field programmable gate array (FPGA) implementation of the advanced encryption standard (AES) algorithm to provide data security. This work does not depend on the look up tables (LUTs) for the implementation the SubBytes and InvSubBytes stages of transformations of the AES encryption and decryption; this new architecture uses combinational logical circuits for implementing SubBytes and InvSubBytes transformation. Due to the elimination of LUTs, unwanted delays are eliminated in this architecture and a subpipelining structure is introduced for improving the speed of the AES algorithm. Here, modified positive polarity reed muller (MPPRM) architecture is inserted to reduce the total hardware requirements, and comparisons are made with different implementations. With MPPRM architecture introduced in SubBytes stages, an efficient mixcolumn and invmixcolumn architecture that is suited to subpipelined round units is added. The performances of the proposed AES-MPPRM architecture is analyzed in terms of number of slice registers, flip flops, number of slice LUTs, number of logical elements, slices, bonded IOB, operating frequency and delay. There are five different AES architectures including LAES, AES-CTR, AES-CFA, AES-BSRD, and AES-EMCBE. The LUT of the AES-MPPRM architecture designed in the Spartan 6 is reduced up to 15.45% when compared to the AES-BSRD.


2014 ◽  
Vol 573 ◽  
pp. 181-186 ◽  
Author(s):  
G.P. Ramesh ◽  
A. Rajan

—Field-programmable gate array (FPGA) optimized random number generators (RNGs) are more resource-efficient than software-optimized RNGs because they can take advantage of bitwise operations and FPGA-specific features. A random number generator (RNG) is a computational or physical device designed to generate a sequence of numbers or symbols that lack any pattern, i.e. appear random. The many applications of randomness have led to the development of several different methods for generating random data. Several computational methods for random number generation exist, but often fall short of the goal of true randomness though they may meet, with varying success, some of the statistical tests for randomness intended to measure how unpredictable their results are (that is, to what degree their patterns are discernible).LUT-SR Family of Uniform Random Number Generators are able to handle randomness only based on seeds that is loaded in the look up table. To make random generation efficient, we propose new approach based on SRAM storage device.Keywords: RNG, LFSR, SRAM


AIChE Journal ◽  
2014 ◽  
Vol 60 (3) ◽  
pp. 1013-1026 ◽  
Author(s):  
Taha Mohseni Ahooyi ◽  
Masoud Soroush ◽  
Jeffrey E. Arbogast ◽  
Warren D. Seider ◽  
Ulku G. Oktem

2013 ◽  
Vol 22 (10) ◽  
pp. 3791-3806 ◽  
Author(s):  
Vladimir A. Krylov ◽  
Gabriele Moser ◽  
Sebastiano B. Serpico ◽  
Josiane Zerubia

2014 ◽  
Vol 10 (S306) ◽  
pp. 316-318
Author(s):  
Iftach Sadeh

AbstractLarge photometric galaxy surveys allow the study of questions at the forefront of science, such as the nature of dark energy. The success of such surveys depends on the ability to measure the photometric redshifts of objects (photo-zs), based on limited spectral data. A new major version of the public photo-z estimation software, ANNz, is presented here. The new code incorporates several machine-learning methods, such as artificial neural networks and boosted decision/regression trees, which are all used in concert. The objective of the algorithm is to dynamically optimize the performance of the photo-z estimation, and to properly derive the associated uncertainties. In addition to single-value solutions, the new code also generates full probability density functions in two independent ways.


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