Design and analysis of buffer and bufferless routing based NoC for high throughput and low latency communication on FPGA

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Sujata S.B. ◽  
Anuradha M. Sandi
Keyword(s):  
Power Consumption ◽  
High Throughput ◽  
Data Communication ◽  
Injection Rate ◽  
Area Network ◽  
Verilog Hdl ◽  
Content Type ◽  
Chip Area ◽  
And Performance ◽  
On Chip

Purpose The small area network for data communication within routers is suffering from storage of packet, throughput, latency and power consumption. There are a lot of solutions to increase speed of commutation and optimization of power consumption; one among them is Network-on-chip (NoC). In the literature, there are several NoCs which can reconfigurable dynamically and can easily test and validate the results on FPGA. But still, NoCs have limitations which are regarding chip area, reconfigurable time and throughput. Design/methodology/approach To address these limitations, this research proposes the dynamically buffered and bufferless reconfigurable NoC (DB2R NoC) using X-Y algorithm for routing, Torus for switching and Flexible Direction Order (FDOR) for direction finding between source and destination nodes. Thus, the 3 × 3 and 4 × 4 DB2R NoCs are made free from deadlock, low power and latency and high throughput. To prove the applicability and performance analysis of DB2R NoC for 3 × 3 and 4 × 4 routers on FPGA, the 22 bits for buffered and 19 bit for bufferless designs have been successfully synthesized using Verilog HDL and implemented on Artix-7 FPGA development bond. The virtual input/output chips cope pro tool has been incorporated in the design to verify and debug the complete design on Artix-7 FPGA. Findings In the obtained result, it has been found that 35% improvement in throughput, 23% improvement in latency and 47% optimization in area has been made. The complete design has been tested for 28 packets of injection rate 0.01; the packets have been generated by using NLFSR. Originality/value In the obtained result, it has been found that 35% improvement in throughput, 23% improvement in latency and 47% optimization in area has been made. The complete design has been tested for 28 packets of injection rate 0.01; the packets have been generated by using NLFSR.

scholarly journals Fuzzy-Based Thermal Management Scheme for 3D Chip Multicores with Stacked Caches

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 346 ◽  
Author(s):  
Lili Shen ◽  
Ning Wu ◽  
Gaizhen Yan
Keyword(s):  
Power Consumption ◽  
Thermal Management ◽  
System Performance ◽  
Control Policy ◽  
Three Dimension ◽  
Processor Core ◽  
Management Scheme ◽  
And Performance ◽  
On Chip ◽  
Silicon Vias

By using through-silicon-vias (TSV), three dimension integration technology can stack large memory on the top of cores as a last-level on-chip cache (LLC) to reduce off-chip memory access and enhance system performance. However, the integration of more on-chip caches increases chip power density, which might lead to temperature-related issues in power consumption, reliability, cooling cost, and performance. An effective thermal management scheme is required to ensure the performance and reliability of the system. In this study, a fuzzy-based thermal management scheme (FBTM) is proposed that simultaneously considers cores and stacked caches. The proposed method combines a dynamic cache reconfiguration scheme with a fuzzy-based control policy in a temperature-aware manner. The dynamic cache reconfiguration scheme determines the size of the cache for the processor core according to the application that reaches a substantial amount of power consumption savings. The fuzzy-based control policy is used to change the frequency level of the processor core based on dynamic cache reconfiguration, a process which can further improve the system performance. Experiments show that, compared with other thermal management schemes, the proposed FBTM can achieve, on average, 3 degrees of reduction in temperature and a 41% reduction of leakage energy.

scholarly journals Design techniques for passive wireless microsystems

2021 ◽  
Author(s):  
Xiongliang Lai
Keyword(s):  
Power Consumption ◽  
Transmission Rate ◽  
Data Communication ◽  
Modulation Scheme ◽  
Voltage Level ◽  
Passive Wireless Microsystems ◽  
Level Shifters ◽  
Wireless Microsystems ◽  
On Chip ◽  
Design Techniques

The unique advantage of harvesting power wirelessly has evolved passive wireless microsystems to a fast-growing high-impact technology. In this dissertation, several new design techniques are proposed for the increasingly stringent requirements of passive wireless microsystems. The absence of on-board batteries imposes ultralow power consumption of passive wireless microsystems. Recent research reveals that multi-voltage systems-on-a-chip dramatically reduce power consumption such that power-efficient on-chip voltage level shifters are critically needed. This dissertation proposes a novel set of voltage level shifters built upon diode-based clamper-rectifier configurations. The voltage level shifters are passively powered by incoming signals with no static current consumption and are able to shift the incoming signals bidirectionally to suit the different voltage domains. The shifting steps could be continuous and are not bounded by the discrete transistor thresholds and power rails. A second bottleneck of passive wireless microsystems is the wireless power-harvesting efficiency that limits the wireless communication distance and the on-chip circuitry complexity and functionality. This dissertation proposes a transformer-based impedance matching network that greatly improves the power transfer efficiency from the receiving antenna to the on-chip circuit loads. The transformer is also capable of automatically calibrating its input impedance to match to the antenna impedance by a novel low-power varactor current tuning technique. In passive wireless microsystems, data modulation scheme largely determines the power transmission efficiency and data communication speed. Exploiting the constant carrier envelop of FSK modulation, this dissertation proposes a dual-tank architecture for FSK receivers in passive wireless microsystems. The dual receiving tanks significantly improves the power conversion efficiency of on-chip AC-to-DC voltage multipliers by providing high-quality-factor resonating tank voltages at each of the alternating FSK carriers. High data transmission rate is also achieved by exploring the dual tanks in an all-digital and a voltage-level shifting FSK demodulators.

Reducing the number of passing links in the 2D-NoC for performance and reliability improvement

2020 ◽  
Vol 17 (5) ◽  
pp. 621-632
Author(s):  
Seyyed Javad Seyyed Mahdavi Chabok ◽  
Seyed Amin Alavi
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Network Reliability ◽  
Telecommunication Network ◽  
High Reliability ◽  
Routing Algorithm ◽  
Network Size ◽  
Content Type ◽  
Probability Of Collision ◽  
On Chip

Purpose The routing algorithm is one of the most important components in designing a network-on-chip (NoC). An effective routing algorithm can cause better performance and throughput, and thus, have less latency, lower power consumption and high reliability. Considering the high scalability in networks and fault occurrence on links, the more the packet reaches the destination (i.e. to cross the number of fewer links), the less the loss of packets and information would be. Accordingly, the proposed algorithm is based on reducing the number of passed links to reach the destination. Design/methodology/approach This paper presents a high-performance NoC that increases telecommunication network reliability by passing fewer links to destination. A large NoC is divided into small districts with central routers. In such a system, routing in large routes is performed through these central routers district by district. Findings By reducing the number of links, the number of routers also decreases. As a result, the power consumption is reduced, the performance of the NoC is improved, and the probability of collision with a faulty link and network latency is decreased. Originality/value The simulation is performed using the Noxim simulator because of its ability to manage and inject faults. The proposed algorithm, XY routing, as a conventional algorithm for the NoC, was simulated in a 14 × 14 network size, as the typical network size in the recent works.

A Novel Optimization Approach Based on Scratchpad Memory for Mobile LBS

2013 ◽  
Vol 325-326 ◽  
pp. 935-938
Author(s):  
Rui Xin Hu ◽  
Wei Hu ◽  
Ze Yu Zuo ◽  
Min Wang ◽  
Jing Xu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Mobile Devices ◽  
Rapid Development ◽  
Main Memory ◽  
Optimization Approach ◽  
Performance Requirement ◽  
Scratchpad Memory ◽  
Frequency Of Use ◽  
And Performance ◽  
On Chip

With the popularization of mobile broadband network, mobile devices have been used more wildly in recent years. As an important part of mobile services, LBS (Location Based Service) also has rapid development for such devices. However, LBS on mobile devices will consume more energy and mobile users have more restrict performance requirement than before. As an important part of on-chip memory, scratchpad memory (SPM) has less power-consumption and higher performance for SPM is controlled by software and without extra tags. In this paper, we proposed a novel optimization approach based SPM for mobile LBS to reduce the power-consumption and improve the performance of the application. According to our approach, SPM is used as the on-chip main memory to contain the data with high frequency of use. The experimental results show that SPM can optimize the mobile LBS both on power-consumption and performance.

scholarly journals Design techniques for passive wireless microsystems

2021 ◽  
Author(s):  
Xiongliang Lai
Keyword(s):  
Power Consumption ◽  
Transmission Rate ◽  
Data Communication ◽  
Modulation Scheme ◽  
Voltage Level ◽  
Passive Wireless Microsystems ◽  
Level Shifters ◽  
Wireless Microsystems ◽  
On Chip ◽  
Design Techniques

The unique advantage of harvesting power wirelessly has evolved passive wireless microsystems to a fast-growing high-impact technology. In this dissertation, several new design techniques are proposed for the increasingly stringent requirements of passive wireless microsystems. The absence of on-board batteries imposes ultralow power consumption of passive wireless microsystems. Recent research reveals that multi-voltage systems-on-a-chip dramatically reduce power consumption such that power-efficient on-chip voltage level shifters are critically needed. This dissertation proposes a novel set of voltage level shifters built upon diode-based clamper-rectifier configurations. The voltage level shifters are passively powered by incoming signals with no static current consumption and are able to shift the incoming signals bidirectionally to suit the different voltage domains. The shifting steps could be continuous and are not bounded by the discrete transistor thresholds and power rails. A second bottleneck of passive wireless microsystems is the wireless power-harvesting efficiency that limits the wireless communication distance and the on-chip circuitry complexity and functionality. This dissertation proposes a transformer-based impedance matching network that greatly improves the power transfer efficiency from the receiving antenna to the on-chip circuit loads. The transformer is also capable of automatically calibrating its input impedance to match to the antenna impedance by a novel low-power varactor current tuning technique. In passive wireless microsystems, data modulation scheme largely determines the power transmission efficiency and data communication speed. Exploiting the constant carrier envelop of FSK modulation, this dissertation proposes a dual-tank architecture for FSK receivers in passive wireless microsystems. The dual receiving tanks significantly improves the power conversion efficiency of on-chip AC-to-DC voltage multipliers by providing high-quality-factor resonating tank voltages at each of the alternating FSK carriers. High data transmission rate is also achieved by exploring the dual tanks in an all-digital and a voltage-level shifting FSK demodulators.

scholarly journals Design of on-chip temperature-based digital signal processing for customized wireless microcontroller

2019 ◽  
Vol 14 (2) ◽  
pp. 653
Author(s):  
S.F. R. Faezal ◽  
M. N. Isa ◽  
S. Taking ◽  
S. N. Mohyar ◽  
A. B. Jambek ◽  
...  
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Digital Signal ◽  
System On Chip ◽  
Processing Unit ◽  
Verilog Hdl ◽  
Chip Design ◽  
Chip Area ◽  
Monitoring Process ◽  
On Chip

<span>Dramatic rises in power density and die sizes inside system-on-chip (SoC) design have led to the thermal issue. High temperatures or uneven temperature distributions may result not only in reliability issues, also has become the biggest issue that can limit the system performance.  This paper presents the design and simulation of a temperature-based digital signal processing unit for modern system-on-chip design using the Verilog HDL. This design provides continuous monitoring of temperature and reacts to specified conditions. The simulation of the system has been done on Synopsys Software. The result showed that temperature monitoring process is within the temperature range due to the incorporation of an interrupt-based system and with an advantage of minimum chip area required.</span>

An FPGA Implementation of On Chip UART Testing with BIST Techniques

2016 ◽  
Vol 5 (3) ◽  
pp. 176 ◽  
Author(s):  
P Bala Gopal ◽  
K Hari Kishore
Keyword(s):  
Short Distance ◽  
Serial Communication ◽  
Data Communication ◽  
Full Duplex ◽  
Communication Link ◽  
Verilog Hdl ◽  
Self Test ◽  
Chip Testing ◽  
On Chip ◽  
And Control

A Universal Asynchronous Receiver Transmitter (UART) is usually implemented for asynchronous serial communication, mostly used for short distance communications. It allows full duplex serial communication link and is used in data communication and control system. Nowadays there is a requirement for on chip testing to overcome the product failures. This paper targets the introduction of Built-in self test (BIST) for UART to overcome the above two constraints of testability and data integrity. The 8-bit UART with BIST module is coded in Verilog HDL and synthesized and simulated using Xilinx XST and implemented on SPARTAN 3E FPGA. Results indicate that this model eliminates the need for expensive testers and thereby it can reduce the development time and cost.

An Investigation on the Effects of Subnet Extension on Delay and Throughput in Network-on-Chip

2015 ◽  
Vol 25 (02) ◽  
pp. 1650015 ◽  
Author(s):  
Mostafa Haghi ◽  
Abdolrasoul Ghasemi ◽  
Saed Moradi
Keyword(s):  
Performance Evaluation ◽  
High Throughput ◽  
Injection Rate ◽  
Network On Chip ◽  
System On Chip ◽  
Low Delay ◽  
Delay Cycle ◽  
On Chip ◽  
Two Parameters ◽  
Level Performance

When designing a system-on-chip (SOC), a network-on-chip (NOC) paradigm is the backbone of used interconnection, but in recent years, with a great improvement in silicon technology and the ability to implement billions of transistors on a wafer, it sounds that wire-based communication is not efficient any longer, therefore designers intend to replace wireless transferring data methodology instead. In the following, we show how the performance of the wireless network is improved with subnet extension. This paper focuses on the evaluation of delay and throughput which are two important factors in network proficiency. In fact, to enhance the performance of the system, we need to reduce the number of delay cycles and improve the throughput, therefore to keep balance between these two parameters, designer has to adjust the packet injection rate (PIR) in a safe margin such that it does not exceed a certain point in each state, otherwise delay is uncontrollable, thus it is required to clearly identify the take-off points. About the designer also has to be informed purpose for which the system is going to be designed. It strictly depends on whether high throughput or low delay cycle is desirable. Subnet extension is a way to achieve this target. Here, totally three networks with the number of cores 64, 512 and 1024 have been selected, respectively. The effect of subnet extension is evaluated on each one. The behavior of each network with different number of subnets and IPs is studied. Obtained results from the simulator for different ranges of PIR and subnets are significant. To emphasize, we highlight the take-off points for the delay cycles and the points which does not cross the PIR level. Performance evaluation is conducted based on flit-accurate and open source system C simulator BookSim.

scholarly journals Virtual channel organization and arbitration for network on chip router architecure

2021 ◽  
Author(s):  
Masoud Oveis Gharan
Keyword(s):  
Network On Chip ◽  
Input Port ◽  
Virtual Channel ◽  
Chip Area ◽  
Theoretical Concepts ◽  
Real Time Traffic ◽  
Systems On Chip ◽  
Physical Channel ◽  
And Performance ◽  
On Chip

The advent of Multi-Processor Systems-on-Chip (MPSoC) has emphasized the importance of on-chip communication infrastructures. Network on Chip (NoC) has emerged as a state of the art paradigm for efficient on-chip communication. Among the various components employed in NoC routers, Virtual Channel (VC) plays an important role in the performance and hardware requirements of an NoC system. The VC mechanism enables the multiplexing and buffering of several packets to travel over a single physical channel concurrently. VC arbitration (or arbiter) is another critical organization component of a router that has significant impact on the efficiency of an NoC system. Arbiter performs arbitration among the group of VCs that are competing for a single resource (e.g. output-port). In this dissertation, we propose novel approaches for dynamic VC flow control mechanism and VC arbitration. The first two approaches are based on the adaptivity of VCs in the router input-port that improves the efficiency of NoC system. In both of techniques, the input-port comprises of a centralized buffer whose slots are dynamically allocated to VCs according to a real-time traffic situation. The performance improvement is achieved by utilizing multiple virtual channels with minimal buffer resources. The VC arbitration approach is based on an efficient and fast arbiter that functions upon the index of its input-ports (or VC requests). The architecture of arbiter scales with the Log2 of the number of inputs where a conventional round robin arbiter scales with the number of inputs. The index based behavior and the architecture of our arbiter leads to lower power consumption and chip area. This dissertation presents the organizations and micro-architectures of NoC routers. We have employed SystemVerilog at the micro-architectural level design and modeling of NoC components. We employ three CAD platforms namely ModelSim, Quartus (FPGA) and Synopsys (ASIC level) to design, simulate and implement our router based NoCs. The simulation results support the theoretical concepts of our proposed VC organization and arbitration approaches. We have also implemented and conducted simulation and modeling experiments for conventional VC organization and arbitration models. The experimental results verify the efficiency of our proposed models in terms of power, area and performance in different NoC configurations.

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