scholarly journals Parallel impelementation of RC6 algorithm

2021 ◽  
Vol 3 (2) ◽  
pp. 01-09
Author(s):  
Artan Berisha ◽  
Hektor Kastrati

Data security is very important in the field of Computer Science. In this paper the encryption algorithm called RC6 will be analyzed and its standard and parallel implementation will be done. First the field of Cryptology is discussed in general terms, then the classification of encryption algorithms according to operation and techniques is explained. RC6 is a symmetric block algorithm derived from the RC5 algorithm. RC6 operates on 128-bit blocks and accepts 128, 192, 256-bit keys until 2040 bytes. In the Advanced Encryption Standard (AES) competition, RC6 managed to rank among the five finalists. The structure of the RC6 algorithm will be analyzed also the encryption and decryption methods.  The comparison between standard and parallel implementation will be made.

2021 ◽  
Vol 10 (2) ◽  
pp. 21-30
Author(s):  
Ahmida ABIODUN ◽  
Olanrewaju LAWAL ◽  
Oyediran OYEBIYI ◽  
Odiete JOSEPH ◽  
Adeyemi ADETORO

Data security is a key aspect of today’s communication trend and growth. Various mechanisms have been developed to achieve this security. One is cryptography, which represents a most effective method of enhancing security and confidentiality of data. In this work, a hybrid based 136bit key algorithm involving a sequential combination of XOR (Exclusive –Or) encryption and AES (Advanced Encryption Standard) algorithm to enhance the security strength is developed. The hybrid algorithm performance is matched with XOR encryption and AES algorithm using encryption and decryption time, throughput of encryption, space complexity and CPU process time.


2017 ◽  
Vol 4 ◽  
pp. 82-86
Author(s):  
Dawid Górniak ◽  
Piotr Kopniak

The data is often the most valuable thing that we collect on our computers. Without proper data security with encryption our valuable information may be illegally used by an unauthorised person. The article presents selected encryption methods and hash functions available in Boucy Castle library for Java programming language. The presented analysis applies to measurement of the speed of signature generation and verification. The signatures are for 240 bit encryption algorithms. In case of a hash function, the analysis refers to the speed of such functions. The fastest encryption algorithm and hash function from the research group were AES and SHA1.


Author(s):  
Mourad Talbi ◽  
Med Salim Bouhalel

The IoT Internet of Things being a promising technology of the future. It is expected to connect billions of devices. The increased communication number is expected to generate data mountain and the data security can be a threat. The devices in the architecture are fundamentally smaller in size and low powered. In general, classical encryption algorithms are computationally expensive and this due to their complexity and needs numerous rounds for encrypting, basically wasting the constrained energy of the gadgets. Less complex algorithm, though, may compromise the desired integrity. In this paper we apply a lightweight encryption algorithm named as Secure IoT (SIT) to a quantized speech image for Secure IoT. It is a 64-bit block cipher and requires 64-bit key to encrypt the data. This quantized speech image is constructed by first quantizing a speech signal and then splitting the quantized signal into frames. Then each of these frames is transposed for obtaining the different columns of this quantized speech image. Simulations result shows the algorithm provides substantial security in just five encryption rounds.


Cryptography ◽  
2020 ◽  
pp. 129-141
Author(s):  
Filali Mohamed Amine ◽  
Gafour Abdelkader

Advanced Encryption Standard is one of the most popular symmetric key encryption algorithms to many works, which have employed to implement modified AES. In this paper, the modification that has been proposed on AES algorithm that has been developed to decrease its time complexity on bulky data and increased security will be included using the image as input data. The modification proposed itself including alteration in the mix column and shift rows transformation of AES encryption algorithm, embedding confusion-diffusion. This work has been implemented on the most recent Xilinx Spartan FPGA.


Symmetry ◽  
2019 ◽  
Vol 11 (2) ◽  
pp. 293 ◽  
Author(s):  
Sreeja Rajesh ◽  
Varghese Paul ◽  
Varun Menon ◽  
Mohammad Khosravi

Recent advancements in wireless technology have created an exponential rise in the number of connected devices leading to the internet of things (IoT) revolution. Large amounts of data are captured, processed and transmitted through the network by these embedded devices. Security of the transmitted data is a major area of concern in IoT networks. Numerous encryption algorithms have been proposed in these years to ensure security of transmitted data through the IoT network. Tiny encryption algorithm (TEA) is the most attractive among all, with its lower memory utilization and ease of implementation on both hardware and software scales. But one of the major issues of TEA and its numerous developed versions is the usage of the same key through all rounds of encryption, which yields a reduced security evident from the avalanche effect of the algorithm. Also, the encryption and decryption time for text is high, leading to lower efficiency in IoT networks with embedded devices. This paper proposes a novel tiny symmetric encryption algorithm (NTSA) which provides enhanced security for the transfer of text files through the IoT network by introducing additional key confusions dynamically for each round of encryption. Experiments are carried out to analyze the avalanche effect, encryption and decryption time of NTSA in an IoT network including embedded devices. The results show that the proposed NTSA algorithm is much more secure and efficient compared to state-of-the-art existing encryption algorithms.


Author(s):  
Filali Mohamed Amine ◽  
Gafour Abdelkader

Advanced Encryption Standard is one of the most popular symmetric key encryption algorithms to many works, which have employed to implement modified AES. In this paper, the modification that has been proposed on AES algorithm that has been developed to decrease its time complexity on bulky data and increased security will be included using the image as input data. The modification proposed itself including alteration in the mix column and shift rows transformation of AES encryption algorithm, embedding confusion-diffusion. This work has been implemented on the most recent Xilinx Spartan FPGA.


Complexity ◽  
2021 ◽  
Vol 2021 ◽  
pp. 1-13
Author(s):  
Mohammad Kamrul Hasan ◽  
Muhammad Shafiq ◽  
Shayla Islam ◽  
Bishwajeet Pandey ◽  
Yousef A. Baker El-Ebiary ◽  
...  

As the world keeps advancing, the need for automated interconnected devices has started to gain significance; to cater to the condition, a new concept Internet of Things (IoT) has been introduced that revolves around smart devicesʼ conception. These smart devices using IoT can communicate with each other through a network to attain particular objectives, i.e., automation and intelligent decision making. IoT has enabled the users to divide their household burden with machines as these complex machines look after the environment variables and control their behavior accordingly. As evident, these machines use sensors to collect vital information, which is then the complexity analyzed at a computational node that then smartly controls these devicesʼ operational behaviors. Deep learning-based guessing attack protection algorithms have been enhancing IoT security; however, it still has a critical challenge for the complex industries’ IoT networks. One of the crucial aspects of such systems is the need to have a significant training time for processing a large dataset from the networkʼs previous flow of data. Traditional deep learning approaches include decision trees, logistic regression, and support vector machines. However, it is essential to note that this convenience comes with a price that involves security vulnerabilities as IoT networks are prone to be interfered with by hackers who can access the sensor/communication data and later utilize it for malicious purposes. This paper presents the experimental study of cryptographic algorithms to classify the types of encryption algorithms into the asymmetric and asymmetric encryption algorithm. It presents a deep analysis of AES, DES, 3DES, RSA, and Blowfish based on timing complexity, size, encryption, and decryption performances. It has been assessed in terms of the guessing attack in real-time deep learning complex IoT applications. The assessment has been done using the simulation approach and it has been tested the speed of encryption and decryption of the selected encryption algorithms. For each encryption and decryption, the tests executed the same encryption using the same plaintext for five separate times, and the average time is compared. The key size used for each encryption algorithm is the maximum bytes the cipher can allow. To the comparison, the average time required to compute the algorithm by the three devices is used. For the experimental test, a set of plaintexts is used in the simulation—password-sized text and paragraph-sized text—that achieves target fair results compared to the existing algorithms in real-time deep learning networks for IoT applications.


Author(s):  
Subhi R. M. Zeebaree

Nowadays there is a lot of importance given to data security on the internet. The DES is one of the most preferred block cipher encryption/decryption procedures used at present. This paper presents a high throughput reconfigurable hardware implementation of DES Encryption algorithm. This achieved by using a new proposed implementation of the DES algorithm using pipelined concept.  The implementation of the proposed design is presented by using Spartan-3E (XC3S500E) family FPGAs and is one of the fastest hardware implementations with much greater security. At a clock frequency of 167.448MHz for encryption and 167.870MHz for decryption, it can encrypt or decrypt data blocks at a rate of 10688Mbps.


Data transmission with protection is main concept which is getting demand now a days for which number of encryption of data techniques are developed and now in this paper Advanced Encryption Standard (AES) Algorithm is used and is implemented on FPGA kit using vertex-3 family. We use 128 bits consists of input, key data, output data for this design. It is called an iterative looping with replacement box, key, loop in this design for both encryption and decryption of data. We use Xilinx software platform for simulation of our design that is AES by which area utilization and throughput is increased for achieving low power consumption, high data security, reduced latency and easy architectural design. This data operation is applicable in many areas.


Sign in / Sign up

Export Citation Format

Share Document