Investigation of STI diodes as electrostatic discharge (ESD) protection devices in deep submicron (DSM) CMOS process

2013 ◽  
Author(s):  
Thomas Au ◽  
Marek Syrzycki
Keyword(s):  
Electrostatic Discharge ◽  
Deep Submicron ◽  
Cmos Process ◽  
Esd Protection ◽  
Protection Devices

scholarly journals CDM Protection Test Structure for I/O Cells in a Submicronic Technology

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 443
Author(s):  
Mihaela-Daniela Dobre ◽  
Philippe Coll ◽  
Gheorghe Brezeanu
Keyword(s):  
Electrostatic Discharge ◽  
New Technology ◽  
Test Chip ◽  
Technology Node ◽  
Ground Resistance ◽  
Maximum Resistance ◽  
Device Model ◽  
Protection Method ◽  
Esd Protection ◽  
Protection Devices

This paper proposes an investigation of a CDM (charge device model) electrostatic discharge (ESD) protection method used in submicronic input–output (I/O) structures. The modeling of the commonly used ESD protection devices as well as the modeling of the breakdown caused by ESD is not accurate using traditional commercial tools, hence the need for test-chip implementation, whenever a new technology node is used in production. The proposed method involves defining, implementing, testing, and concluding on one test-chip structure named generically “CDM ground resistance”. The structure assesses the maximum ground resistance allowed for the considered technology for which CDM protection is assured. The findings are important because they will be actively used as CDM protection for all I/O structures developed in the considered submicronic technology node. The paper will conclude on the constraints in terms of maximum resistance of ground metal track allowed to be CDM protected.

Damage analysis in smart-power technology electrostatic discharge (ESD) protection devices

1999 ◽  
Vol 39 (6-7) ◽  
pp. 1143-1148 ◽  
Author(s):  
D. Pogany ◽  
N. Seliger ◽  
M. Litzenberger ◽  
H. Gossner ◽  
M. Stecher ◽  
...  
Keyword(s):  
Electrostatic Discharge ◽  
Damage Analysis ◽  
Smart Power ◽  
Esd Protection ◽  
Protection Devices

scholarly journals Area-Efficient Embedded Resistor-Triggered SCR with High ESD Robustness

Electronics ◽  
2019 ◽  
Vol 8 (4) ◽  
pp. 445
Author(s):  
Hou ◽  
Du ◽  
Yang ◽  
Liu ◽  
Liu
Keyword(s):  
Electrostatic Discharge ◽  
Cmos Process ◽  
Silicon Area ◽  
Lateral Dimension ◽  
Esd Protection ◽  
Layout Area ◽  
Protection Capability ◽  
P Type ◽  
Area Efficient

The trigger voltage of the direct-connected silicon-controlled rectifier (DCSCR) was effectively reduced for electrostatic discharge (ESD) protection. However, a deep NWELL (DNW) is required to isolate PWELL from P-type substrate (PSUB) in DCSCR, which wastes part of the layout area. An area-efficient embedded resistor-triggered silicon-controlled rectifier (ERTSCR) is proposed in this paper. As verified in a 0.3-μm CMOS process, the proposed ERTSCR exhibits lower triggering voltage due to series diode chains and embedded deep n-well resistor in the trigger path. Additionally, the proposed ERTSCR has a failure current of more than 5 A and a corresponding HBM ESD robustness of more than 8 KV. Furthermore, compared with the traditional DCSCR, to sustain the same ESD protection capability, the proposed ERTSCR will consume 10% less silicon area by fully utilizing the lateral dimension in the deep n-well extension region, while the proposed ERTSCR has a larger top metal width.

Design of 2.4-GHz T/R switch with embedded ESD protection devices in CMOS process

2017 ◽  
Vol 78 ◽  
pp. 258-266
Author(s):  
Chun-Yu Lin ◽  
Rui-Hong Liu ◽  
Ming-Dou Ker
Keyword(s):  
Cmos Process ◽  
Esd Protection ◽  
Protection Devices

ESD Robustness Designs for the HV Power DEMOS

2012 ◽  
Vol 271-272 ◽  
pp. 1286-1290
Author(s):  
Shen Li Chen ◽  
Chi Ling Chu
Keyword(s):  
High Voltage ◽  
Electrostatic Discharge ◽  
Unit Area ◽  
The Other ◽  
Esd Protection ◽  
Protection Devices ◽  
Protection Circuits

Two kinds of efficient electrostatic discharge (ESD) protection circuits in lateral drain extended MOSFETs (DEMOSFETs) will be designed and investigated in this paper. One kind of these test samples is fabricated with an SCR structure, which has the lowest turned-on resistance when it is triggered by a high voltage of ESD event. The SCR circuit is the most efficient of all protection devices in terms of ESD performance per unit area. Furthermore, the other type of these DUTs is an SCR with RC-triggered structure, which will have a small trigger voltage (Vt1) under ESD event, and then it obtains a good ESD immunity level.

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