scholarly journals Self-Adaptive Run-Time Variable Floating-Point Precision for Iterative Algorithms: A Joint HW/SW Approach

Electronics ◽  
2021 ◽  
Vol 10 (18) ◽  
pp. 2209
Author(s):  
Noureddine Ait Said ◽  
Mounir Benabdenbi ◽  
Katell Morin-Allory
Keyword(s):  
Power Consumption ◽  
Execution Time ◽  
Energy Savings ◽  
Iterative Algorithms ◽  
Time Variable ◽  
Floating Point ◽  
Double Precision ◽  
Time Saving ◽  
Variable Precision ◽  
Run Time

Using standard Floating-Point (FP) formats for computation leads to significant hardware overhead since these formats are over-designed for error-resilient workloads such as iterative algorithms. Hence, hardware FP Unit (FPU) architectures need run-time variable precision capabilities. In this work, we propose a new method and an FPU architecture that enable designers to dynamically tune FP computations’ precision automatically at run-time called Variable Precision in Time (VPT), leading to significant power consumption, execution time, and energy savings. In spite of its circuit area overhead, the proposed approach simplifies the integration of variable precision in existing software workloads at any level of the software stack (OS, RTOS, or application-level): it only requires lightweight software support and solely relies on traditional assembly instructions, without the need for a specialized compiler or custom instructions. We apply the technique on the Jacobi and the Gauss–Seidel iterative methods taking full advantage of the suggested FPU. For each algorithm, two modified versions are proposed: a conservative version and a relaxed one. Both algorithms are analyzed and compared statistically to understand the effects of VPT on iterative applications. The implementations demonstrate up to 70.67% power consumption saving, up to 59.80% execution time saving, and up to 88.20% total energy saving w.r.t the reference double precision implementation, and with no accuracy loss.

scholarly journals Area and Power Efficient Fused Floating-point Dot Product Unit based on Radix-2r Multiplier & Pipeline Feedforward-Cutset-Free Carry-Lookahead Adder

2021 ◽  
Vol 9 (2) ◽  
pp. 782-788
Author(s):  
M. Madhu Babu, K. Rama Naidu
Keyword(s):  
Power Consumption ◽  
Execution Time ◽  
Floating Point ◽  
Double Precision ◽  
Power Efficient ◽  
Dot Product ◽  
Power Delay Product ◽  
Dsp Applications ◽  
Standard Library

Fused floating point operations play a major role in many DSP applications to reduce operational area & power consumption. Radix-2r multiplier (using 7-bit encoder technique) & pipeline feedforward-cutset-free carry-lookahead  adder(PFCF-CLA) are used to enhance the traditional FDP unit. Pipeline concept is also infused into system to get the desired pipeline fused floating-point dot product (PFFDP) operations. Synthesis results are obtained using 60nm standard library with 1GHz clock. Power consumption of single & double precision operations are 2.24mW & 3.67mW respectively. The die areas are 27.48 mm2 , 46.72mm2 with an execution time of 1.91 ns , 2.07 ns for a single & double precision operations respectively. Comparison with previous data has also been performed. The area-delay product(ADP) & power-delay product(PDP) of our proposed architecture are 18%,22% & 27%,18% for single and double precision operations respectively.

scholarly journals Online Signature Verification Systems on a Low-Cost FPGA

2021 ◽  
Vol 12 (1) ◽  
pp. 378
Author(s):  
Enrique Cantó Navarro ◽  
Rafael Ramos Lara ◽  
Mariano López García
Keyword(s):  
Embedded System ◽  
Execution Time ◽  
Low Cost ◽  
Computing System ◽  
Floating Point ◽  
Signature Verification ◽  
Double Precision ◽  
Hardware Accelerator ◽  
Online Signature ◽  
Online Signature Verification

This paper describes three different approaches for the implementation of an online signature verification system on a low-cost FPGA. The system is based on an algorithm, which operates on real numbers using the double-precision floating-point IEEE 754 format. The double-precision computations are replaced by simpler formats, without affecting the biometrics performance, in order to permit efficient implementations on low-cost FPGA families. The first approach is an embedded system based on MicroBlaze, a 32-bit soft-core microprocessor designed for Xilinx FPGAs, which can be configured by including a single-precision floating-point unit (FPU). The second implementation attaches a hardware accelerator to the embedded system to reduce the execution time on floating-point vectors. The last approach is a custom computing system, which is built from a large set of arithmetic circuits that replace the floating-point data with a more efficient representation based on fixed-point format. The latter system provides a very high runtime acceleration factor at the expense of using a large number of FPGA resources, a complex development cycle and no flexibility since it cannot be adapted to other biometric algorithms. By contrast, the first system provides just the opposite features, while the second approach is a mixed solution between both of them. The experimental results show that both the hardware accelerator and the custom computing system reduce the execution time by a factor ×7.6 and ×201 but increase the logic FPGA resources by a factor ×2.3 and ×5.2, respectively, in comparison with the MicroBlaze embedded system.

scholarly journals A Simple Model for Portable and Fast Prediction of Execution Time and Power Consumption of GPU Kernels

2021 ◽  
Vol 18 (1) ◽  
pp. 1-25
Author(s):  
Lorenz Braun ◽  
Sotirios Nikas ◽  
Chen Song ◽  
Vincent Heuveline ◽  
Holger Fröning
Keyword(s):  
Simple Model ◽  
Power Consumption ◽  
Execution Time ◽  
Fast Prediction

scholarly journals Estimation Accuracy on Execution Time of Run-Time Tasks in a Heterogeneous Distributed Environment

Sensors ◽  
2016 ◽  
Vol 16 (9) ◽  
pp. 1386 ◽  
Author(s):  
Qi Liu ◽  
Weidong Cai ◽  
Dandan Jin ◽  
Jian Shen ◽  
Zhangjie Fu ◽  
...  
Keyword(s):  
Execution Time ◽  
Estimation Accuracy ◽  
Distributed Environment ◽  
Run Time

scholarly journals Research on IEEE 754 Standard Single Precision Floating Point Multipliers Designed using Urdhva Triyagbhyam Sutra of Vedic Mathematics

2019 ◽  
Vol 8 (2S11) ◽  
pp. 2990-2993
Keyword(s):  
Floating Point ◽  
Double Precision ◽  
Single Precision ◽  
Vedic Mathematics ◽  
Quadruple Precision

Duplication of the coasting element numbers is the big activity in automated signal handling. So the exhibition of drifting problem multipliers count on a primary undertaking in any computerized plan. Coasting factor numbers are spoken to utilizing IEEE 754 modern day in single precision(32-bits), Double precision(sixty four-bits) and Quadruple precision(128-bits) organizations. Augmentation of those coasting component numbers can be completed via using Vedic generation. Vedic arithmetic encompass sixteen wonderful calculations or Sutras. Urdhva Triyagbhyam Sutra is most usually applied for growth of twofold numbers. This paper indicates the compare of tough work finished via exceptional specialists in the direction of the plan of IEEE 754 ultra-modern-day unmarried accuracy skimming thing multiplier the usage of Vedic technological statistics.

scholarly journals Innovative approaches and methods to the implementation of energy-saving measures and technologies at mining enterprises

2021 ◽  
Vol 288 ◽  
pp. 01109
Author(s):  
Alexander Semenov ◽  
Yuriy Bebikhov ◽  
Ayaal Egorov ◽  
Vladislav Shevchuk ◽  
Marina Glazun ◽  
...  
Keyword(s):  
Power Consumption ◽  
Mathematical Simulation ◽  
Energy Saving ◽  
Electric Drive ◽  
Economic Benefit ◽  
Energy Savings ◽  
Reactive Power ◽  
Specific Power ◽  
Specific Power Consumption ◽  
Instrumental Monitoring

The paper presents the evaluation of the implementation of innovative methods of energy savings in electric drive and power supply systems at mining enterprises. The evaluation involves mathematical simulation and instrumental monitoring of the defined indicators that allow obtaining a multiplier economic benefit through the appropriate approach to the implementation and subsequent exploitation of energy-saving technologies. For this purpose, the potential of energy savings in industry in general, and at mining enterprises in particular, is shown. Such indicators as power consumption in mining, the dynamics of power losses in public grids, specific power consumption for lighting and household needs, specific power consumption for lifting and supplying water, as well as for sewage treatment were evaluated. As an example, such measures as reactive power compensation, the introduction of frequency-controlled electric drive systems, the development and implementation of the systems for continuous monitoring of power quality indicators were considered pointwise (at some sites of enterprises). The mathematical simulation method was implemented using the MatLab software package. The instrumental monitoring was carried for 7 days with a ten-minute interval. As a result of the assessment of such measures, the total economic benefit approaching to 9.0 million rubles a year was obtained.

DPF-ECC: A Framework for Efficient ECC with Double Precision Floating-Point Computing Power

2021 ◽  
pp. 1-1
Author(s):  
Lili Gao ◽  
Fangyu Zheng ◽  
Rong Wei ◽  
Jiankuo Dong ◽  
Niall Emmart ◽  
...  
Keyword(s):  
Floating Point ◽  
Double Precision ◽  
Computing Power
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