scholarly journals Design of a 41.14–48.11 GHz Triple Frequency Based VCO

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 529 ◽  
Author(s):  
Abbas Nasri ◽  
Siroos Toofan ◽  
Motahhareh Estebsari ◽  
Abouzar Estebsari
Keyword(s):  
Power Systems ◽  
Phase Noise ◽  
Communication Systems ◽  
Power Grids ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Class Ab ◽  
Triple Frequency ◽  
Measurement Units ◽  
Almost All

Growing deployment of more efficient communication systems serving electric power grids highlights the importance of designing more advanced intelligent electronic devices and communication-enabled measurement units. In this context, phasor measurement units (PMUs) are being widely deployed in power systems. A common block in almost all PMUs is a phase locked oscillator which uses a voltage controlled oscillator (VCO). In this paper, a triple frequency based voltage controlled oscillator is presented with low phase noise and robust start-up. The VCO consists of a detector, a comparator, and triple frequency. A VCO starts-up in class AB, then steadies oscillation in class C with low current oscillation. The frequency of the VCO, which is from 13.17 GHz to 16.03 GHz, shows that the frequency is tripling to 41.14–48.11 GHz. Therefore, its application is not limited to PMUs. This work has been simulated in a standard 0.18 µm CMOS process. The simulated VCO achieves a phase noise of −99.47 dBc/Hz at 1 MHz offset and −121.8 dBc/Hz at 10 MHz offset from the 48.11 GHz carrier.

Design and analysis of a low noise CMOS charge pump phase locked loop circuit

2021 ◽  
pp. 2140002
Author(s):  
Yanbo Chen ◽  
Shubin Zhang
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Low Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Output Frequency ◽  
Power Supply Voltage ◽  
Supply Noise

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

A Scalable Millimetre-Wave Differential CMOS Cross-Coupled VCO for Automotive Radar Application

2018 ◽  
Vol 27 (10) ◽  
pp. 1850158 ◽  
Author(s):  
Rekha Yadav ◽  
Pawan Kumar Dahiya ◽  
Rajesh Mishra
Keyword(s):  
Phase Noise ◽  
Oxide Semiconductor ◽  
Control Voltage ◽  
Cmos Process ◽  
Operating Voltage ◽  
Voltage Controlled Oscillator ◽  
Automotive Radar ◽  
Millimetre Wave ◽  
The Impact ◽  
Lc Vco

In this paper, a novel method to realize LC Voltage-Controlled-Oscillator (LC-VCO) operating at 76.2–76.7[Formula: see text]GHz frequency band for microwave RFIC component is presented. The model of cross-coupled differential LC-VCO is designed in 45[Formula: see text]nm technology using Complementary Metal Oxide Semiconductor (CMOS) process for Frequency Modulated Carrier Wave (FMCW) automotive radar sensors and RF transceivers application. The impact of VDD, control voltage and temperature variation on frequency shift, phase noise, and output power has been analyzed to optimize the trade-off between frequency, phase noise, and power requirement. The results depict that LC-VCO dissipates 10.45[Formula: see text]mW power at an operating voltage of 1.5[Formula: see text]V. The phase noise has been observed to be [Formula: see text]90[Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset at 76[Formula: see text]GHz carrier frequency. The estimated layout area of IC is [Formula: see text]m2. The result shows the edge of the design over existing techniques.

A 2.3 mW Multi-Frequency Clock Generator with −137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology

2019 ◽  
Vol 29 (08) ◽  
pp. 2050130 ◽  
Author(s):  
Jagdeep Kaur Sahani ◽  
Anil Singh ◽  
Alpana Agarwal
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Dead Zone ◽  
Dynamic Logic ◽  
Cmos Technology ◽  
Control Voltage ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Cmos Inverter ◽  
Digital Cmos

A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency range of 0.025–1.6[Formula: see text]GHz, targeting various SoC applications. The proposed PFD, designed using CMOS dynamic logic, is fast and improves the locking time, dead zone and blind zone in the PLL. The standard CMOS inverter gate-based pseudo differential VCO is used in the PLL. Also, CMOS inverter is used as variable capacitor to tune the frequency of VCO with control voltage. The proposed PLL is designed in a 180[Formula: see text]nm CMOS process with supply voltage of 1.8[Formula: see text]V. The phase noise of VCO is [Formula: see text][Formula: see text]dBc/Hz at an offset frequency of 100[Formula: see text]MHz. The reference clock of 25[Formula: see text]MHz synthesizes the output clock of 1.6[Formula: see text]GHz with rms jitter of 0.642[Formula: see text]ps.

scholarly journals A Very Low-phase-noise CMOS Ring VCO Intended for Sensor Interfaces

2021 ◽  
Author(s):  
Mahin Esmaeilzadeh ◽  
Yves Audet ◽  
Mohamed Ali ◽  
Mohamad Sawan
Keyword(s):  
Phase Noise ◽  
Tuning Range ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Silicon Area ◽  
Wide Range ◽  
Extended Frequency ◽  
Sensor Interfaces ◽  
Low Phase Noise ◽  
Analytical Expressions

<p>We describe in the paper a ring voltage-controlled oscillator (VCO) indicating an improved phase noise over a wide range of frequency offsets and an extended frequency/voltage tuning range. The phase noise is improved by leveraging a better linearity approach, while reducing the VCO gain and maintaining wide tuning range. The proposed VCO is a block of a time-domain comparator embedded in a monitoring and readout circuit of an industrial sensor interface. An analytical model is extracted resulting in closed-form expressions for both input-referred noise and phase noise of the VCO. Employing the analytical expressions, the contributed noise and phase noise limitations are fully addressed, and all the effective factors are investigated. The prototype of the proposed VCO was implemented and fabricated in a 0.35 µm CMOS process. The integrated VCO consumes 0.903 mW from a 3.3 V supply, when running at its maximum frequency of 9.37 MHz. The measured phase noise of the proposed VCO is -147.57 dBc/Hz at 1 MHz offset from the 9.37 MHz oscillation frequency, and the occupied silicon area of circuit is 0.005 mm<sup>2</sup>.</p>

scholarly journals A Design of Wide-Range and Low Phase Noise Linear Transconductance VCO with 193.76 dBc/Hz FoMT for mm-Wave 5G Transceivers

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 935 ◽  
Author(s):  
Arash Hejazi ◽  
YoungGun Pu ◽  
Kang-Yoon Lee
Keyword(s):  
Phase Noise ◽  
Carrier Frequency ◽  
Tuning Range ◽  
Frequency Tuning ◽  
Cmos Process ◽  
Switched Capacitor ◽  
Voltage Controlled Oscillator ◽  
Wide Range ◽  
Layout Area ◽  
Low Phase Noise

This paper presents a wide-range and low phase noise mm-Wave Voltage Controlled Oscillator (VCO) based on the transconductance linearization technique. The proposed technique eliminates the deep triode region of the active part of the VCO, and lowers the noise introduced by the gm-cell. The switch sizes inside the switched capacitor bank of the VCO are optimized to minimize the resistance of the switches while keeping the wide tuning range. A new layout technique shortens the routing of the VCO outputs, and lowers the parasitic inductance and resistance of the VCO routing. The presented method prevents the reduction of the quality factor of the tank due to the long routing. The proposed VCO achieves a discrete frequency tuning range, of 14 GHz to 18 GHz, through a linear coarse and middle switched capacitor array, and offers superior phase noise performance compared to recent state-of-the-art VCO architectures. The design is implemented in a 45 nm CMOS process and occupies a layout area (including output buffers) of 0.14 mm2. The power consumption of the VCO core is 24 mW from the power supply of 0.8 V. The post-layout simulation result shows the VCO achieves the phase noise performances of −87.2 dBc/Hz and −113 dBc/Hz, at 100 kHz and 1 MHz offset frequencies from the carrier frequency of 14 GHz, respectively. In an 18 GHz carrier frequency, the results are −87.4 dBc/Hz and −110 dBc/Hz, accordingly.

A 400 μW Near-Threshold Feedback Class-C VCO with Auto Amplitude Control

2018 ◽  
Vol 27 (05) ◽  
pp. 1850072
Author(s):  
Chenggang Yan ◽  
Chen Hu
Keyword(s):  
Low Power ◽  
Phase Noise ◽  
Feedback Loop ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Amplitude Control ◽  
Ultra Low Power ◽  
Class C ◽  
Low Phase Noise ◽  
Near Threshold

A 400[Formula: see text][Formula: see text]W near-threshold supply class-C voltage controlled oscillator (VCO) with amplitude feedback loop and auto amplitude control (AAC) is proposed in this paper. The amplitude feedback loop and AAC ensure the robust startup of the proposed VCO and automatically adapts it to the class-C mode in steady state. Consequently, ultra-low power can be achieved in AAC mode and low phase noise, high swing can be achieved in AAC off mode. The proposed VCO with AAC gets ultra-low power consumption by limiting the oscillating amplitude and driving the proposed VCO into the deep Class-C mode. Additionally, the peak value detector is employed in this work to boost the controlling voltage of capacitors bank. Thus, a low on resistance of switch transistors is obtained, which increases the Q value of capacitors bank. The simulated phase noise is [Formula: see text]124.5[Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset with the 1.16[Formula: see text]GHz oscillation frequency. In this case, the figure-of-merit including tuning range (FOMT) of proposed VCO is [Formula: see text]195[Formula: see text]dBc/Hz. The proposed VCO is fabricated in SMIC 40[Formula: see text]nm CMOS process and consumes 0.62[Formula: see text]mA from 0.65[Formula: see text]V supply. The measured phase noise is [Formula: see text]109[Formula: see text]dBc/Hz and FOMT is [Formula: see text]179[Formula: see text]dBc/Hz.

scholarly journals 28 GHz balanced pHEMT VCO with low phase noise and high output power performance for 5G mm-Wave systems

2020 ◽  
Vol 10 (5) ◽  
pp. 4623 ◽  
Author(s):  
Abdelhafid Es-saqy ◽  
Maryam Abata ◽  
Mahmoud Mehdi ◽  
Said Mazer ◽  
Mohammed Fattah ◽  
...  
Keyword(s):  
Phase Noise ◽  
Output Power ◽  
Integrated Circuit ◽  
Communication Systems ◽  
Second Harmonic ◽  
Wireless Communication Systems ◽  
Voltage Controlled Oscillator ◽  
Power Performance ◽  
Harmonic Rejection ◽  
Low Phase Noise

This paper presents the study and design of a balanced voltage controlled oscillator VCO for 5G wireless communication systems. This circuit is designed in monolithic microwave integrated circuit (MMIC) technology using PH15 process from UMS foundry. The VCO ensures an adequate tuning range by a single-ended pHEMT varactors configuration. The simulation results show that this circuit delivers a sinusoidal signal of output power around 9 dBm with a second harmonic rejection between 25.87 and 33.83 dB, the oscillation frequency varies between 26.46 and 28.90 GHz, the phase noise is -113.155 and -133.167 dBc/Hz respectively at 1 MHz and 10 MHz offset and the Figure of Merit is -181.06 dBc/Hz. The power consumed by the VCO is 122 mW. The oscillator layout with bias and RF output pads occupies an area of 0.515 mm2.

Low Phase Noise and Low Power Voltage-Controlled-Oscillator Using Current-Reuse Techniques for Wireless Communication Circuits

2013 ◽  
Vol 479-480 ◽  
pp. 1010-1013
Author(s):  
Tsung Han Han ◽  
Meng Ting Hsu ◽  
Cheng Chuan Chung
Keyword(s):  
Low Power ◽  
Phase Noise ◽  
Supply Voltage ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Chip Area ◽  
Voltage Controlled Oscillators ◽  
Communication Circuits ◽  
5 Ghz ◽  
Low Phase Noise

In this paper, we present low phase noise and low power of the voltage-controlled oscillators (VCOs) for 5 GHz applications. This chip is implemented by Taiwan Semiconductor Manufacturing Company (TSMC) standard 0.18 μm CMOS process. The designed circuit topology is included a current-reused configuration. It is adopted memory-reduced tail transistor technique. At the supply voltage 1.5 v, the measured output phase noise is-116.071 dBc/Hz at 1MHz offset frequency from the carrier frequency 5.2 GHz. The core power consumption is 3.7 mW, and tuning range of frequency is about 1.3 GHz from 4.8 to 6.1 GHz. The chip area is 826.19 × 647.83 um2.

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