scholarly journals DrawerPipe: A Reconfigurable Pipeline for Network Processing on FPGA-Based SmartNIC

Electronics ◽  
2019 ◽  
Vol 9 (1) ◽  
pp. 59 ◽  
Author(s):  
Junnan Li ◽  
Zhigang Sun ◽  
Jinli Yan ◽  
Xiangrui Yang ◽  
Yue Jiang ◽  
...  

In the public cloud, FPGA-based SmartNICs are widely deployed to accelerate network functions (NFs) for datacenter operators. We argue that with the trend of network as a service (NaaS) in the cloud is also meaningful to accelerate tenant NFs to meet performance requirements. However, in pursuit of high performance, existing work such as AccelNet is carefully designed to accelerate specific NFs for datacenter providers, which sacrifices the flexibility of rapidly deploying new NFs. For most tenants with limited hardware design ability, it is time-consuming to develop NFs from scratch due to the lack of a rapidly reconfigurable framework. In this paper, we present a reconfigurable network processing pipeline, i.e., DrawerPipe, which abstracts packet processing into multiple “drawers” connected by the same interface. NF developers can easily share existing modules with other NFs and simply load core application logic in the appropriate “drawer” to implement new NFs. Furthermore, we propose a programmable module indexing mechanism, namely PMI, which can connect “drawers” in any logical order, to perform distinct NFs for different tenants or flows. Finally, we implemented several highly reusable modules for low-level packet processing, and extended four example NFs (firewall, stateful firewall, load balancer, IDS) based on DrawerPipe. Our evaluation shows that DrawerPipe can easily offload customized packet processing to FPGA with high performance up to 100 Mpps and ultra-low latency (<10 µs). Moreover, DrawerPipe enables modular development of NFs, which is suitable for rapid deployment of NFs. Compared with individual NF development, DrawerPipe reduces the line of code (LoC) of the four NFs above by 68%.

Author(s):  
Dmitry Victorovich Larin ◽  
Aleksandr Igorevich Getman

Network stacks currently implemented in operating systems can no longer cope with the packet rates offered by 10 Gbit Ethernet. Thus, frameworks were developed claiming to offer a faster alternative for this demand. These frameworks enable arbitrary packet processing systems to be built from commodity hardware handling a traffic rate of several 10 Gbit interfaces, entering a domain previously only available to custom-built hardware. In this paper, we survey various frameworks for high-performance packet IO and their interaction with a modular frameworks and specialized virtual network functions software for high-speed packet processing. We introduce a model to estimate and assess the performance of these packet processing frameworks. Moreover, we analyze the performance of the most prominent frameworks based on representative measurements in packet capturing scenarios. Therefore, we provide a comparison between them and select the area of applicability.


Micromachines ◽  
2021 ◽  
Vol 12 (2) ◽  
pp. 169
Author(s):  
Mengcheng Wang ◽  
Shenglin Ma ◽  
Yufeng Jin ◽  
Wei Wang ◽  
Jing Chen ◽  
...  

Through Silicon Via (TSV) technology is capable meeting effective, compact, high density, high integration, and high-performance requirements. In high-frequency applications, with the rapid development of 5G and millimeter-wave radar, the TSV interposer will become a competitive choice for radio frequency system-in-package (RF SIP) substrates. This paper presents a redundant TSV interconnect design for high resistivity Si interposers for millimeter-wave applications. To verify its feasibility, a set of test structures capable of working at millimeter waves are designed, which are composed of three pieces of CPW (coplanar waveguide) lines connected by single TSV, dual redundant TSV, and quad redundant TSV interconnects. First, HFSS software is used for modeling and simulation, then, a modified equivalent circuit model is established to analysis the effect of the redundant TSVs on the high-frequency transmission performance to solidify the HFSS based simulation. At the same time, a failure simulation was carried out and results prove that redundant TSV can still work normally at 44 GHz frequency when failure occurs. Using the developed TSV process, the sample is then fabricated and tested. Using L-2L de-embedding method to extract S-parameters of the TSV interconnection. The insertion loss of dual and quad redundant TSVs are 0.19 dB and 0.46 dB at 40 GHz, respectively.


2016 ◽  
Vol 51 (4) ◽  
pp. 67-81 ◽  
Author(s):  
Antoine Kaufmann ◽  
SImon Peter ◽  
Naveen Kr. Sharma ◽  
Thomas Anderson ◽  
Arvind Krishnamurthy

2016 ◽  
Vol 44 (2) ◽  
pp. 67-81 ◽  
Author(s):  
Antoine Kaufmann ◽  
SImon Peter ◽  
Naveen Kr. Sharma ◽  
Thomas Anderson ◽  
Arvind Krishnamurthy

2021 ◽  
Vol 13 (3) ◽  
pp. 78
Author(s):  
Chuanhong Li ◽  
Lei Song ◽  
Xuewen Zeng

The continuous increase in network traffic has sharply increased the demand for high-performance packet processing systems. For a high-performance packet processing system based on multi-core processors, the packet scheduling algorithm is critical because of the significant role it plays in load distribution, which is related to system throughput, attracting intensive research attention. However, it is not an easy task since the canonical flow-level packet scheduling algorithm is vulnerable to traffic locality, while the packet-level packet scheduling algorithm fails to maintain cache affinity. In this paper, we propose an adaptive throughput-first packet scheduling algorithm for DPDK-based packet processing systems. Combined with the feature of DPDK burst-oriented packet receiving and transmitting, we propose using Subflow as the scheduling unit and the adjustment unit making the proposed algorithm not only maintain the advantages of flow-level packet scheduling algorithms when the adjustment does not happen but also avoid packet loss as much as possible when the target core may be overloaded Experimental results show that the proposed method outperforms Round-Robin, HRW (High Random Weight), and CRC32 on system throughput and packet loss rate.


2002 ◽  
Vol 41 (3) ◽  
pp. 341-354 ◽  
Author(s):  
Tressie Wright Muldrow ◽  
Timothy Buckley ◽  
Brigitte W. Schay

2020 ◽  
Vol 17 (1) ◽  
Author(s):  
Vânia Rodrigues ◽  
Sérgio Deusdado

AbstractThe discovery of diagnostic or prognostic biomarkers is fundamental to optimize therapeutics for patients. By enhancing the interpretability of the prediction model, this work is aimed to optimize Leukemia diagnosis while retaining a high-performance evaluation in the identification of informative genes. For this purpose, we used an optimal parameterization of Kernel Logistic Regression method on Leukemia microarray gene expression data classification, applying metalearners to select attributes, reducing the data dimensionality before passing it to the classifier. Pearson correlation and chi-squared statistic were the attribute evaluators applied on metalearners, having information gain as single-attribute evaluator. The implemented models relied on 10-fold cross-validation. The metalearners approach identified 12 common genes, with highest average merit of 0.999. The practical work was developed using the public datamining software WEKA.


Author(s):  
Salvatore Di Girolamo ◽  
Andreas Kurth ◽  
Alexandru Calotoiu ◽  
Thomas Benz ◽  
Timo Schneider ◽  
...  

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