scholarly journals An Impedance Source Multi-Level Three Phase Inverter with Common Mode Voltage Elimination and Dead Time Compensation

Electronics ◽  
2020 ◽  
Vol 9 (10) ◽  
pp. 1639
Author(s):  
Mehrdad Mahmoudian ◽  
Maziyar Fakhraei ◽  
Edris Pouresmaeil ◽  
Eduardo M. G. Rodrigues
Keyword(s):  
High Efficiency ◽  
Dead Time ◽  
Harmonic Distortion ◽  
Common Mode ◽  
Current Harmonics ◽  
Pulse Width Modulated ◽  
Switching Algorithm ◽  
Common Mode Voltage ◽  
Power Switches ◽  
Drive Systems

Currently, most electro-mechanical drive systems that require speed control use pulse-width modulated (PWM) variable frequency drives known as adjustable speed drives (ASD). The high switching speeds of the electronics switches are essential for proper operation of the ASD. Common mode voltage (CMV) has its origin in the PWM switching. The CMV increases the stress on the coils and windings, reduces the life of the bearing and, therefore, has a significant impact on motor life cycle. In this paper, a variant of a PWM-based space vector modulation (SVPWM) switching algorithm is proposed to control both the shoot-through intervals and the dead time of the power switches that could be compensated. The proposed algorithm is implemented on a platform consisting of an impedance source network in the DC side of the topology with the purpose of mitigating the CMV and capability of voltage boosting. Since similar methods have achieved a CMV reduction of 1/6 of the DC link voltage so far, in this paper, while surpassing the disturbing current harmonics, the high efficiency is fully accessible. The presented experimental results verify the effectiveness of the proposed approach by slightly increasing the total harmonic distortion (THD) and reducing the converter losses.

Analytical study and simulation of a transformer-less photovoltaic grid-connected inverter with a delta-type tri-direction clamping cell for leakage current elimination

2018 ◽  
Vol 37 (2) ◽  
pp. 814-831 ◽  
Author(s):  
Tohid Jalilzadeh ◽  
Mehrdad Tarafdar Hagh ◽  
Mehran Sabahi
Keyword(s):  
Power Systems ◽  
Leakage Current ◽  
Control Method ◽  
Harmonic Distortion ◽  
Common Mode ◽  
Content Type ◽  
Low Leakage ◽  
Common Mode Voltage ◽  
Power Switches ◽  
The Common

PurposeThis paper aims to propose a new transformer-less inverter structure to reduce the common-mode leakage current in grid-connected photovoltaic (PV) systems. Design/methodology/approachThe proposed circuit structure is the same as the conventional full-bridge inverter with three additional power switches in a triangular structure. These three power switches are between the bridge and the output filter, and they mitigate the common-mode leakage current flowing toward the PV panels’ capacitors. The common-mode leakage current mitigation is done through the three-direction clamping cell (TDCC) concept. By clamping the common-mode voltage to the middle voltage of the DC-link capacitors, the leakage current and the total harmonic distortion (THD) of the injected current to the grid is effectively reduced. Therefore, the efficiency is improved. FindingsThe switching modes and the control method are introduced. A comparison is carried out between the proposed structure and other solutions in the literature. The proposed topology and its respective control method are simulated by PSCAD/EMTDC software. The simulation results validate the advantages of the presented structure such as clamping the common-mode voltage and reducing leakage current and THD of injected current to the grid. Originality/valuePresenting a single phase-improved inverter structure with low-leakage current for grid-connected PV power systems represents a significant original contribution to this work. The proposed structure can inject a sinusoidal current with low THD to the AC grid, and the power factor is unity on the AC side. In the half positive cycle, one of the switches in the TDCC is turned off under zero current. Besides, one of the other switches in TDCC is turned on with zero voltage and, therefore, its turn-on switching losses are zero. The efficiency of the proposed topology is high because of the reduction of leakage current and power losses. Accordingly, the presented topology can be a good solution to the leakage current elimination.

scholarly journals Common-Mode Voltage Harmonic Reduction in Variable Speed Drives Applying a Variable-Angle Carrier Phase-Displacement PWM Method

Energies ◽  
2021 ◽  
Vol 14 (10) ◽  
pp. 2929
Author(s):  
Abraham Marquez Alcaide ◽  
Vito Giuseppe Monopoli ◽  
Xuchen Wang ◽  
Jose I. Leon ◽  
Giampaolo Buticchi ◽  
...  
Keyword(s):  
Carrier Phase ◽  
Harmonic Distortion ◽  
Harmonic Spectrum ◽  
Hydraulic Systems ◽  
Variable Speed ◽  
Common Mode ◽  
Variable Speed Drives ◽  
Phase Displacement ◽  
Common Mode Voltage ◽  
External Component

Electric variable speed drives (VSD) have been replacing mechanic and hydraulic systems in many sectors of industry and transportation because of their better performance and reduced cost. However, the electric systems still face the issue of being considered less reliable than the mechanical ones. For this reason, researchers have been actively investigating effective ways to increase the reliability of such systems. This paper is focused on the analysis of the common-mode voltage (CMV) generated by the operation of the VSDs which directly affects to the lifetime and reliability of the complete system. The method is based on the mathematical description of the harmonic spectrum of the CMV depending on the PWM method implementation. A generalized PWM method where the carriers present a variable phase-displacement is developed. As a result of the presented analysis, the CMV reduction is achieved by applying the PWM method with optimal carrier phase-displacement angles without any external component and/or passive filtering technique. The optimal values of the carrier phase-displacement angles are obtained considering the minimization of the CMV total harmonic distortion. The resulting method is easily implementable on mostly off-the-shelf mid-range micro-controller control platforms. The strategy has been evaluated in a scaled-down experimental setup proving its good performance.

scholarly journals A New Approach to the PWM Modulation for the Multiphase Matrix Converters Supplying Loads with Open-End Winding

Energies ◽  
2021 ◽  
Vol 14 (2) ◽  
pp. 466
Author(s):  
Pawel Szczepankowski ◽  
Natalia Strzelecka ◽  
Enrique Romero-Cadaval
Keyword(s):  
Pulse Width Modulation ◽  
Harmonic Distortion ◽  
Simulation Software ◽  
Common Mode ◽  
New Approach ◽  
Matrix Converters ◽  
Load Voltage ◽  
Common Mode Voltage ◽  
The Common ◽  
Open End Winding

This article presents three variants of the Pulse Width Modulation (PWM) for the Double Square Multiphase type Conventional Matrix Converters (DSM-CMC) supplying loads with the open-end winding. The first variant of PWM offers the ability to obtain zero value of the common-mode voltage at the load’s terminals and applies only six switches within the modulation period. The second proposal archives for less Total Harmonic Distortion (THD) of the generated load voltage. The third variant of modulation concerns maximizing the voltage transfer ratio, minimizing the number of switching, and the common-mode voltage cancellation. The discussed modulations are based on the concept of sinusoidal voltage quadrature signals, which can be an effective alternative to the classic space-vector approach. In the proposed approach, the geometrical arrangement of basic vectors needed to synthesize output voltages is built from the less number of vectors, which is equal to the number of the matrix converter’s terminals. The PWM duty cycle computation is performed using only a second-order determinant of the voltages coordinate matrix without using trigonometric functions. A new approach to the PWM duty cycles computing and the load voltage synthesis by 5 × 5 and 12 × 12 topologies has been verified using the PSIM simulation software.

scholarly journals A Novel Low Common-Mode Voltage Modulation Strategy for ANPC-5L Inverter

2020 ◽  
Vol 185 ◽  
pp. 01015
Author(s):  
Fusheng Wang ◽  
Sai Weng ◽  
Lizhong Ye ◽  
Tao Chen
Keyword(s):  
Harmonic Distortion ◽  
Output Current ◽  
Space Vector ◽  
Common Mode ◽  
Common Mode Voltage ◽  
Zero Sequence ◽  
Implementation Method ◽  
Bus Voltage ◽  
Vector Modulation ◽  
Zero Sequence Voltage

In order to suppress the leakage current of the active neutral point clamed five-level (ANPC-5L) inverter, this paper proposes a novel low common-mode voltage (CMV) modulation strategy based on the space vector modulation thought. Only the 55 voltage vectors with low CMV amplitude instead of all 125 voltage vectors are utilized. The CMV amplitude is suppressed to one-twelfth of the DC bus voltage (Vdc). In the simplified five-level space vector diagram, “obtuse triangle” synthesis principle is used to control the CMV changes twice in each carrier cycle, and get lower output current total harmonic distortion (THD). According to the vector thought, a carrier implementation method based on zero sequence voltage injection and carrier splitting is proposed. This method simplifies the calculation and is easy to implement.Simulation results prove the correctness and feasibility of this low CMV modulation strategy.

Minimization of Common-Mode Voltage of Three-Phase Five-Level NPC Inverter Using 3D Space Vector Modulation

2020 ◽  
Vol 29 (14) ◽  
pp. 2050229 ◽  
Author(s):  
Palanisamy Ramasamy ◽  
Vijayakumar Krishnasamy
Keyword(s):  
Dimensional Space ◽  
Three Dimensional ◽  
Harmonic Distortion ◽  
Space Vector Modulation ◽  
Space Vector ◽  
Common Mode ◽  
Common Mode Voltage ◽  
3D Space ◽  
Vector Modulation ◽  
Switching State

In this paper, a three-dimensional Space Vector Modulation (3D SVM) is implemented for minimization of Common-Mode Voltage (CMV) of five-level Neutral Point Clamped (NPC) inverter. The 3D SVM control includes all merits of 2D SVM and provides better control compared to other PWM strategies. The switching state vectors are selected based on the nearest vector Switching State Vector (NSV); it selects the switching vectors which are having the minimum CMV level. It leads to minimization of the bearing voltage and protection of the drive from the damage; also this system reduces the total harmonic distortion. The switching time is calculated by reference vector identification with large and small subcubes tracking and prisms tracking in 3D cubic region. The CMV level with 3D SVM scheme is compared with other PWM methods. The simulation and hardware results are verified using Matlab Simulink and FPGA processor.

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