Reducing Design Margins by Adaptive Compensation for Thermal and Aging Variations

Worst Case ◽

Adaptive Computation ◽

Computation Efficiency ◽

On Chip

Corner-based design and verification are based on worst-case analysis, thus introducing over-pessimism and large area and power overhead and leading to unnecessary energy consumption. Typical case-based design and verification maximize energy efficiency through design margins reduction and adaptive computation, thus helping achieve sustainable computing. Dynamically adapting to manufacturing, environmental, and usage variations is the key to shaving unnecessary design margins, which requires on-chip modules that can sense and configure design parameters both globally and locally to maximize computation efficiency, and maintain this efficiency over the lifetime of the system. This chapter presents an adaptive threshold compensation scheme using a transimpedance amplifier and adaptive body biasing to overcome the effects of temperature variation, reliability degradation, and process variation. The effectiveness and versatility of the scheme are demonstrated with two example applications, one as a temperature aware design to maintain IONto IOFFcurrent ratio, the other as a reliability sensor for NBTI (Negative Bias Temperature Instability).

Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2012.2220573 ◽

2013 ◽

Vol 21 (10) ◽

pp. 1823-1836 ◽

Cited By ~ 54

Author(s):

Yiyuan Xie ◽

Mahdi Nikdast ◽

Jiang Xu ◽

Xiaowen Wu ◽

Wei Zhang ◽

...

Keyword(s):

Optical Networks ◽

Case Analysis ◽

Worst Case Analysis ◽

Crosstalk Noise ◽

Worst Case ◽

Networks On Chip ◽

On Chip

First International Conference on Integration and Commercialization of Micro and Nanosystems, Parts A and B ◽

Investigation of Contribution Ratio Between NBTI and HC Effects in PMOSFETs Under Deep-Submicron Process

10.1115/mnc2007-21082 ◽

2007 ◽

Author(s):

Mu-Chun Wang ◽

Zhen-Ying Hsieh ◽

Shuang-Yuan Chen ◽

Heng-Sheng Huang

Keyword(s):

Drain Current ◽

Gate Oxide ◽

Interface State ◽

Unstable State ◽

Negative Bias ◽

Worst Case ◽

Temperature Instability ◽

Submicron Process

Quantifying the contribution of the hot carrier effect (HCE) and the negative bias temperature instability (NBTI) effect in PMOSFET device reliability is an urgent target, especially as the dual poly-gate implantation and the novel oxide growth recipe is derived. At this stage, the PMOS gate-oxide thickness is thinner than before, therefore, the implanted boron or BF2 is possible to penetrate from poly gate to surface channel. Furthermore, the implant source contains the plenty ionized hydrogen. This material is easily to be trapped in the gate oxide or bonded with the surface-channel silicon. The amount of interface state concentration, Nit, or oxide trap concentration, Not, is increased. As a result, the threshold voltage of the PMOSFET will be shifted away from the design target. Therefore, the source/drain current will be influenced and this PMOSFET will usually exhibit an unstable state. In the worst case, the IC chip will fail or stop working. This negative bias temperature instability (NBTI) effect has the tremendous impact to the PMOSFET performance.

Sensitive, Linear, Robust Current-To-Time Converter Circuit for Vehicle Automation Application

Electronics ◽

10.3390/electronics9030490 ◽

2020 ◽

Vol 9 (3) ◽

pp. 490

Author(s):

Nandakishor Yadav ◽

Youngbae Kim ◽

Mahmoud Alashi ◽

Kyuwon Ken Choi

Keyword(s):

Random Access ◽

Optimization Method ◽

Digital Converter ◽

Large Area ◽

Analog To Digital ◽

Linear Current ◽

Converter Design ◽

Vehicle Automation

Voltage-to-time and current-to-time converters have been used in many recent works as a voltage-to-digital converter for artificial intelligence applications. In general, most of the previous designs use the current-starved technique or a capacitor-based delay unit, which is non-linear, expensive, and requires a large area. In this paper, we propose a highly linear current-to-digital converter. An optimization method is also proposed to generate the optimal converter design containing the smallest number of PMOS and sensitive circuits such as a differential amplifier. This enabled our design to be more stable and robust toward negative bias temperature instability (NBTI) and process variation. The proposed converter circuit implements the point-wise conversion from current-to-time, and it can be used directly for a variety of applications, such as analog-to-digital converters (ADC), used in built-in computational random access (C-RAM) memory. The conversion gain of the proposed circuit is 3.86 ms/A, which is 52 times greater than the conversion gains of state-of-the-art designs. Further, various time-to-digital converter (TDC) circuits are reviewed for the proposed current-to-time converter, and we recommend one circuit for a complete ADC design.

A Learning-Based Framework for Circuit Path Level NBTI Degradation Prediction

Electronics ◽

10.3390/electronics9111976 ◽

2020 ◽

Vol 9 (11) ◽

pp. 1976

Author(s):

Aiguo Bu ◽

Jie Li

Keyword(s):

Timing Analysis ◽

Operating Conditions ◽

Worst Case ◽

Learning Framework ◽

Minimal Loss ◽

Complex Dependence ◽

Speed Up ◽

Tremendous Challenge

Negative bias temperature instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits. Due to its complex dependence on operating conditions, it is a tremendous challenge to the existing timing analysis flow. In order to get the accurate aged delay of the circuit, previous research mainly focused on the gate level or lower. This paper proposes a low-runtime and high-accuracy machining learning framework on the circuit path level firstly, which can be formulated as a multi-input–multioutput problem and solved using a linear regression model. A large number of worst-case path candidates from ISCAS’85, ISCAS’89, and ITC’99 benchmarks were used for training and inference in the experiment. The results show that our proposed approach achieves significant runtime speed-up with minimal loss of accuracy.

Impact of negative and positive bias temperature stress on 6T-SRAM cells

Advances in Radio Science ◽

10.5194/ars-7-191-2009 ◽

2009 ◽

Vol 7 ◽

pp. 191-196 ◽

Cited By ~ 10

Author(s):

S. Drapatz ◽

G. Georgakos ◽

D. Schmitt-Landsiedel

Keyword(s):

Memory Cell ◽

Oxide Materials ◽

Positive Bias ◽

Worst Case ◽

Temperature Instability ◽

High K ◽

Bias Temperature Stress ◽

Degradation Effect

Abstract. With introduction of high-k gate oxide materials, the degradation effect Positive Bias Temperature Instability (PBTI) is starting to play an important role. Together with the still effective Negative Bias Temperature Instability (NBTI) it has significant influence on the 6T SRAM memory cell. We present simulations of both effects, first isolated, then combined in SRAM operation. During long hold of one data, both effects add up to a worst case impact. This leads to an asymmetric cell, which, in a directly following read cycle, combined with the generally unavoidable production variations, maximizes the risk of destructive reading. In future SRAM designs, it will be important to consider this combination of effects to avoid an undesired write event.

Task mapping and routing optimization for hard real-time Networks-on-Chip

Bulletin of Electrical Engineering and Informatics ◽

10.11591/eei.v8i2.1395 ◽

2019 ◽

Vol 8 (2) ◽

pp. 414-421 ◽

Cited By ~ 1

Author(s):

M. Norazizi Sham Mohd Sayuti ◽

Farida Hazwani Mohd Ridzuan ◽

Zul Hilmi Abdullah

Keyword(s):

Real Time ◽

Optimization Technique ◽

Network Routing ◽

Design Parameters ◽

Task Mapping ◽

Evaluation Function ◽

Worst Case ◽

Networks On Chip ◽

On Chip ◽

Hard Real Time

Interference from high priority tasks and messages in a hard real-time Networks-on-Chip (NoC) create computation and communication delays. As the delays increase in number, maintaining the system’s schedulability become difficult. In order to overcome the problem, one way is to reduce interference in the NoC by changing task mapping and network routing. Some population-based heuristics evaluate the worst-case response times of tasks and messages based on the schedulability analysis, but requires a significant amount of optimization time to complete due to the complexity of the evaluation function. In this paper, we propose an optimization technique that explore both parameters simultaneously with the aim to meet the schedulability of the system, hence reducing the optimization time. One of the advantages from our approach is the unrepeated call to the evaluation function, which is unaddressed in the heuristics that configure design parameters in stages. The results show that a schedulable configuration can be found from the large design space.

Vth Extraction Based Run Time Transistor Width (TWOS) Module for On-Chip Negative Bias Temperature Instability (NBTI) Mitigation

Sensor Letters ◽

10.1166/sl.2019.4103 ◽

2019 ◽

Vol 17 (5) ◽

pp. 385-392

Author(s):

Vaibhav Neema ◽

Kuldeep Raguwanshi ◽

Ambika Prasad Shah ◽

Santosh Kumar Vishvakarma

Keyword(s):

Negative Bias ◽

Temperature Instability ◽

Run Time ◽

On Chip

Multilayer Machine Learning-Assisted Optimization-Based Robust Design and Its Applications to Antennas and Arrays

10.36227/techrxiv.12681947 ◽

2020 ◽

Author(s):

Weiqi Chen ◽

Qi Wu ◽

Chen Yu ◽

Haiming Wang ◽

Wei Hong

Keyword(s):

Machine Learning ◽

Design Process ◽

Robust Design ◽

Design Method ◽

Computation Time ◽

Design Parameters ◽

Worst Case Analysis ◽

Worst Case ◽

And Performance ◽

Robust Design Method

An efficient multilayer machine learning-assisted optimization (ML-MLAO)-based robust design method is proposed for antenna and array applications. Machine learning methods are introduced into multiple layers of the robust design process, including worst-case analysis (WCA), maximum input tolerance hypervolume (MITH) searching, and robust optimization, considerably accelerating the whole robust design process. First, based on a surrogate model mapping between the design parameters and performance, WCA is performed using a genetic algorithm to ensure reliability. MITH searching is then carried out using a double-layer MLAO (DL-MLAO) framework to find the MITH of the given design point. Next, based on the training set obtained using DL-MLAO, correlations between the design parameters and the MITH are learned. The robust design is carried out using surrogate models for both the performance and the MITH, and these models are updated online following the ML-MLAO scheme. Furthermore, two examples, including an array synthesis problem and an antenna design problem, are used to verify the proposed ML-MLAO method. Finally, the numerical results and computation time are discussed to demonstrate the effectiveness of the proposed method.

Aging-Aware Task Scheduling for Mesh-Based Network-on-Chips Under Aging Effect

Journal of Circuits System and Computers ◽

10.1142/s0218126619501469 ◽

2019 ◽

Vol 28 (09) ◽

pp. 1950146 ◽

Cited By ~ 1

Author(s):

Jinbin Tu ◽

Tianhao Yang ◽

Lu Yin ◽

Shuangyu Xie ◽

Ruitao Xu ◽

...

Keyword(s):

Task Scheduling ◽

Aging Effect ◽

Performance Degradation ◽

Path Delay ◽

Processor Core ◽

Heuristic Scheduling ◽

Scheduling Method ◽

On Chip

The aging effect induced by negative bias temperature instability (NBTI) is a universal issue existing in electronic equipments. NBTI aging effect can increase the path delay of network-on-chip (NoC) device, resulting in the decreased frequency of processor core and in turn its performance degradation. Under this circumstance, aging-aware task scheduling becomes a complex and challenging problem in advanced multicore systems. This paper presents an aging-aware scheduling method that incorporates NBTI aging effect into the task scheduling framework for mesh-based NoCs. The proposed method relies on a NBTI aging model to evaluate the degradation of core’s operating frequency to establish the task scheduling model under aging effect. Taking into account core performance degradation and the communication overheads among cores, we develop a meta-heuristic scheduling strategy based on particle swarm optimization algorithm to minimize the total execution time of all tasks. Experimental results show that the schedule obtained by the aging-aware algorithm has shorter completion time and higher throughput compared with the nonaging-aware case. On average, the makespan can be reduced by 13.55% and the throughput can be increased by 21.73% for a variety of benchmark applications.