Investigation of Contribution Ratio Between NBTI and HC Effects in PMOSFETs Under Deep-Submicron Process

2007 ◽  
Author(s):  
Mu-Chun Wang ◽  
Zhen-Ying Hsieh ◽  
Shuang-Yuan Chen ◽  
Heng-Sheng Huang
Keyword(s):  
Drain Current ◽  
Gate Oxide ◽  
Interface State ◽  
Unstable State ◽  
Negative Bias ◽  
Negative Bias Temperature Instability ◽  
Worst Case ◽  
Temperature Instability ◽  
Bias Temperature Instability ◽  
Submicron Process

Quantifying the contribution of the hot carrier effect (HCE) and the negative bias temperature instability (NBTI) effect in PMOSFET device reliability is an urgent target, especially as the dual poly-gate implantation and the novel oxide growth recipe is derived. At this stage, the PMOS gate-oxide thickness is thinner than before, therefore, the implanted boron or BF2 is possible to penetrate from poly gate to surface channel. Furthermore, the implant source contains the plenty ionized hydrogen. This material is easily to be trapped in the gate oxide or bonded with the surface-channel silicon. The amount of interface state concentration, Nit, or oxide trap concentration, Not, is increased. As a result, the threshold voltage of the PMOSFET will be shifted away from the design target. Therefore, the source/drain current will be influenced and this PMOSFET will usually exhibit an unstable state. In the worst case, the IC chip will fail or stop working. This negative bias temperature instability (NBTI) effect has the tremendous impact to the PMOSFET performance.

NEGATIVE BIAS TEMPERATURE INSTABILITY IN TIN/HF-SILICATE BASED GATE STACKS

2007 ◽  
Vol 17 (01) ◽  
pp. 129-141
Author(s):  
N. A. CHOWDHURY ◽  
D. MISRA ◽  
N. RAHIM
Keyword(s):  
Interface State ◽  
Initial Time ◽  
Negative Bias ◽  
Gate Stacks ◽  
Negative Bias Temperature Instability ◽  
Threshold Voltage Shift ◽  
Temperature Instability ◽  
Bias Temperature Instability ◽  
High Bias ◽  
The Impact

This work studies the effects of negative bias temperature instability (NBTI) on p-channel MOSFETS with TiN/HfSi x O y (20% SiO 2 based high-κ gate stacks under different gate bias and elevated temperature conditions. For low bias conditions, threshold voltage shift (ΔVT) is most probably due to the mixed degradation within the bulk high-κ. For moderately high bias conditions, H-species dissociation in the presence of holes and subsequent diffusion may be initially responsible for interface state and positively charged bulk trap generation. Initial time, temperature and oxide electric field dependence of ΔVT in our devices shows an excellent match with that of SiO 2 based devices, which is explained by reaction-diffusion (R-D) model of NBTI. Under high bias condition at elevated temperatures, due to higher Si - H bond-annealing/bond-breaking ratio, the experimentally observed absence of the impact ionization induced hot holes at the interfacial layer (IL)/ Si interface probably limits the interface state generation and ΔVT as they quickly reach saturation.

scholarly journals Analysis of the Negative-Bias-Temperature-Instability on Omega-Gate Silicon Nanowire SOI MOSFETs with Different Dimensions

2020 ◽  
Vol 15 (2) ◽  
pp. 1-5
Author(s):  
Vanessa Cristina Pereira da Silva ◽  
Gilson Wirth ◽  
Joao Antonio Martino ◽  
Paula Ghedini Der Agopian
Keyword(s):  
Gate Oxide ◽  
Channel Length ◽  
Advanced Technology ◽  
Negative Bias ◽  
Reliability Parameter ◽  
Negative Bias Temperature Instability ◽  
Temperature Instability ◽  
Bias Temperature Instability ◽  
Simulated Analysis ◽  
Technology Nodes

This work presents an experimental andThis work presents an experimental and simulated analysis of the Negative-Bias-Temperature-Instability (NBTI) on omega-gate nanowire (NW) pMOSFETS transistors, focusing on the influence of channel length and width, since it is an important reliability parameter for advanced technology nodes. To better understand the obtained results of NBTI effect in NW, the 3D-numerical simulations were performed. The results shows a high NBTI in NW (ΔVT≈200-300mV – for WNW=10nm) due to the higher gate oxide electric field accelerating the NBTI effect providing a higher degradation. simulated analysis of the Negative-Bias-Temperature-Instability (NBTI) on omega-gate nanowire (NW) pMOSFETS transistors, focusing on the influence of channel length and width, since it is an important reliability parameter for advanced technology nodes. To better understand the obtained results of NBTI effect in NW, the 3D-numerical simulations were performed. The results shows a high NBTI in NW (ΔVT≈200-300mV – for WNW=10nm) due to the higher gate oxide electric field accelerating the NBTI effect providing a higher degradation.

Negative Bias Temperature Instability on Subthreshold Swing of SiC MOSFET

2017 ◽  
Vol 897 ◽  
pp. 533-536
Author(s):  
Cheng Tyng Yen ◽  
Hsiang Ting Hung ◽  
Chien Chung Hung ◽  
Lurng Shehng Lee ◽  
Chwan Ying Lee ◽  
...  
Keyword(s):  
Room Temperature ◽  
Gate Oxide ◽  
Subthreshold Swing ◽  
Negative Bias ◽  
Negative Bias Temperature Instability ◽  
Temperature Instability ◽  
Bias Temperature Instability ◽  
Hole Trapping ◽  
Charged Interface ◽  
Positively Charged

The NBTI characteristics of SiC MOSFET were studied by the subthreshold swing. The subthreshold swing was found to be very sensitive to the starting bias of transfer curve. The increase of subthreshold swing for MOSFET with poor oxide reached 400% when the starting bias was-15V. The increase of subthreshold swing was caused by enhanced hole trapping which could be explained by the mechanism of positively charged interface states assisted hole trapping. The increase of subthreshold swing for MOSFET with improved gate oxide was reduced to about 40% when the starting bias was-20V and the value approached saturation for starting biases more negative than-10V, which can also be explained by the proposed mechanism. The increase of subthreshold swing for MOSFET with improved oxide was not sensitive to the temperature. The increase of subthreshold swing at 175°C was only 5%~7% higher than that at room temperature.

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