Impact of negative and positive bias temperature stress on 6T-SRAM cells

Abstract. With introduction of high-k gate oxide materials, the degradation effect Positive Bias Temperature Instability (PBTI) is starting to play an important role. Together with the still effective Negative Bias Temperature Instability (NBTI) it has significant influence on the 6T SRAM memory cell. We present simulations of both effects, first isolated, then combined in SRAM operation. During long hold of one data, both effects add up to a worst case impact. This leads to an asymmetric cell, which, in a directly following read cycle, combined with the generally unavoidable production variations, maximizes the risk of destructive reading. In future SRAM designs, it will be important to consider this combination of effects to avoid an undesired write event.

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Defect Creation Stimulated by Thermally Activated Hole Trapping as the Driving Force Behind Negative Bias Temperature Instability in SiO2, SiON, and High-k Gate Stacks

2008 IEEE International Integrated Reliability Workshop Final Report ◽

10.1109/irws.2008.4796094 ◽

2008 ◽

Cited By ~ 7

Author(s):

Tibor Grasser ◽

Ben Kaczer ◽

Thomas Aichinger ◽

Wolfgang Goes ◽

Michael Nelhiebel

Keyword(s):

Driving Force ◽

Negative Bias ◽

Gate Stacks ◽

Negative Bias Temperature Instability ◽

Temperature Instability ◽

Thermally Activated ◽

Bias Temperature Instability ◽

Hole Trapping ◽

High K ◽

Defect Creation

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Positive Bias Temperature Instability Effects in advanced High-k / Metal Gate NMOSFETs

2008 IEEE International Integrated Reliability Workshop Final Report ◽

10.1109/irws.2008.4796085 ◽

2008 ◽

Cited By ~ 2

Author(s):

D.P. Ioannou ◽

S. Mittl ◽

G. LaRosa

Keyword(s):

Positive Bias ◽

Metal Gate ◽

Temperature Instability ◽

Bias Temperature Instability ◽

High K

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Investigation of Contribution Ratio Between NBTI and HC Effects in PMOSFETs Under Deep-Submicron Process

First International Conference on Integration and Commercialization of Micro and Nanosystems, Parts A and B ◽

10.1115/mnc2007-21082 ◽

2007 ◽

Author(s):

Mu-Chun Wang ◽

Zhen-Ying Hsieh ◽

Shuang-Yuan Chen ◽

Heng-Sheng Huang

Keyword(s):

Drain Current ◽

Gate Oxide ◽

Interface State ◽

Unstable State ◽

Negative Bias ◽

Negative Bias Temperature Instability ◽

Worst Case ◽

Temperature Instability ◽

Bias Temperature Instability ◽

Submicron Process

Quantifying the contribution of the hot carrier effect (HCE) and the negative bias temperature instability (NBTI) effect in PMOSFET device reliability is an urgent target, especially as the dual poly-gate implantation and the novel oxide growth recipe is derived. At this stage, the PMOS gate-oxide thickness is thinner than before, therefore, the implanted boron or BF2 is possible to penetrate from poly gate to surface channel. Furthermore, the implant source contains the plenty ionized hydrogen. This material is easily to be trapped in the gate oxide or bonded with the surface-channel silicon. The amount of interface state concentration, Nit, or oxide trap concentration, Not, is increased. As a result, the threshold voltage of the PMOSFET will be shifted away from the design target. Therefore, the source/drain current will be influenced and this PMOSFET will usually exhibit an unstable state. In the worst case, the IC chip will fail or stop working. This negative bias temperature instability (NBTI) effect has the tremendous impact to the PMOSFET performance.

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Impact of the crystallization of the high-k dielectric gate oxide on the positive bias temperature instability of the n-channel metal-oxide-semiconductor field emission transistor

Applied Physics Letters ◽

10.1063/1.4811274 ◽

2013 ◽

Vol 102 (23) ◽

pp. 232909 ◽

Cited By ~ 8

Author(s):

Han Jin Lim ◽

Youngkuk Kim ◽

In Sang Jeon ◽

Jaehyun Yeo ◽

Badro Im ◽

...

Keyword(s):

Metal Oxide ◽

Field Emission ◽

Gate Oxide ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Positive Bias ◽

Temperature Instability ◽

Bias Temperature Instability ◽

High K ◽

High K Dielectric

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New insight on negative bias temperature instability degradation with drain bias of 28nm High-K Metal Gate p-MOSFET devices

Microelectronics Reliability ◽

10.1016/j.microrel.2014.05.010 ◽

2014 ◽

Vol 54 (11) ◽

pp. 2378-2382 ◽

Cited By ~ 6

Author(s):

Miao Liao ◽

Zhenghao Gan

Keyword(s):

Negative Bias ◽

Negative Bias Temperature Instability ◽

Metal Gate ◽

Temperature Instability ◽

Bias Temperature Instability ◽

High K ◽

Drain Bias

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Countermeasures against NBTI degradation on 6T-SRAM cells

Advances in Radio Science ◽

10.5194/ars-9-255-2011 ◽

2011 ◽

Vol 9 ◽

pp. 255-261 ◽

Cited By ~ 8

Author(s):

E. Glocker ◽

D. Schmitt-Landsiedel ◽

S. Drapatz

Keyword(s):

Random Access ◽

Memory Cell ◽

Random Access Memory ◽

Aging Effect ◽

Static Random Access Memory ◽

Negative Bias Temperature Instability ◽

Access Memory ◽

Bias Temperature Instability ◽

Simulation Results ◽

Degradation Effect

Abstract. In current process technologies, NBTI (negative bias temperature instability) has the most severe aging effect on static random access memory (SRAM) cells. This degradation effect causes loss of stability. In this paper countermeasures against this hazard are presented and quantified via simulations in 90 nm process technologies by the established metrics SNMread, SNMhold, Iread and Write Level. With regard to simulation results and practicability best candidates are chosen and, dependent on individual preferences at memory cell design, the best countermeasure in each case is recommended.

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A Modified Architecture for Radix-4 Booth Multiplier with Adaptive Hold Logic

International Journal of Students Research in Technology & Management ◽

10.18510/ijsrtm.2016.411 ◽

2016 ◽

Vol 4 (1) ◽

pp. 01-05

Author(s):

S Suvarna ◽

K Rajesh ◽

T Radhu

Keyword(s):

Threshold Voltage ◽

High Speed ◽

Negative Bias ◽

Positive Bias ◽

Negative Bias Temperature Instability ◽

Discrete Cosine Transforms ◽

Temperature Instability ◽

Booth Multiplier ◽

Bias Temperature Instability ◽

Digital Multipliers

High speed digital multipliers are most efficiently used in many applications such as Fourier transform, discrete cosine transforms, and digital filtering. The throughput of the multipliers is based on speed of the multiplier, and then the entire performance of the circuit depends on it. The pMOS transistor in negative bias cause negative bias temperature instability (NBTI), which increases the threshold voltage of the transistor and reduces the multiplier speed. Similarly, the nMOS transistor in positive bias cause positive bias temperature instability (PBTI).These effects reduce the transistor speed and the system may fail due to timing violations. So here a new multiplier was designed with novel adaptive hold logic (AHL) using Radix-4 Modified Booth Multiplier. By using Radix-4 Modified Booth Encoding (MBE), we can reduce the number of partial products by half. Modified booth multiplier helps to provide higher throughput with low power consumption. This can adjust the AHL circuit to reduce the performance degradation. The expected result will be reduce threshold voltage, increase throughput and speed and also reduce power. This modified multiplier design is coded by Verilog and simulated using Xilinx ISE 12.1 and implemented in Spartan 3E FPGA kit.

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