scholarly journals A Smart Floating Gate Transistor with Two Control Gates for Active Noise Control

Micromachines ◽  
2019 ◽  
Vol 10 (11) ◽  
pp. 722
Author(s):  
Mao ◽  
Yang ◽  
Ma ◽  
Yan ◽  
Zhang
Keyword(s):  
Large Scale ◽  
Noise Control ◽  
Low Cost ◽  
Active Noise Control ◽  
Complementary Metal Oxide Semiconductor ◽  
Floating Gate ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Active Noise ◽  
Floating Gate Transistor

A smart floating gate transistor with two control gates was proposed for active noise control in bioelectrical signal measurement. The device, which is low cost and capable of large-scale integration, was implemented in a standard single-poly complementary metal–oxide–semiconductor (CMOS) process. A model of the device was developed to demonstrate the working principle. Theoretical analysis and simulation results proved the superposition of the two control gates. A series of test experiments were carried out and the results showed that the device was in accordance with the basic electrical characteristics of a floating gate transistor, including the current–voltage (I–V) characteristics and the threshold characteristics observed on the two control gates. Based on the source follower circuit, the experimental results proved that the device can reduce interference by more than 29 dB, which demonstrates the feasibility of the proposed device for active noise control.

Active noise control on a large‐scale ducted fan with inlet wave‐number sensing

2000 ◽  
Vol 107 (5) ◽  
pp. 2800-2801
Author(s):  
Jerome P. Smith ◽  
Ricardo A. Burdisso ◽  
Daniel L. Sutliff ◽  
Laurence J. Heidelberg
Keyword(s):  
Large Scale ◽  
Noise Control ◽  
Active Noise Control ◽  
Wave Number ◽  
Ducted Fan ◽  
Active Noise

Multi-Bit Quantum Dot Nonvolatile Memory (QDNVM) Using Cladded Germanium and Silicon Quantum Dots

2015 ◽  
Vol 24 (03n04) ◽  
pp. 1550003 ◽  
Author(s):  
Murali Lingalugari ◽  
Pik-Yiu Chan ◽  
Evan Heller ◽  
Faquir Jain
Keyword(s):  
Quantum Dots ◽  
Quantum Dot ◽  
Nonvolatile Memory ◽  
Complementary Metal Oxide Semiconductor ◽  
Memory Device ◽  
Floating Gate ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Device Structure ◽  
Nonvolatile Memory Device

In this paper, we are experimentally demonstrating the multi-bit storage of a nonvolatile memory device with cladded quantum dots as the floating gate. These quantum dot nonvolatile memory (QDNVM) devices were fabricated by using standard complementary metal-oxide-semiconductor (CMOS) process. The quantum dots in the floating gate region assembled using site-specific selfassembly (SSA) technique. Quantum mechanical simulations of this device structure are also presented. The experimental results show that the voltage separation between the bits was 0.15V and the voltage pulses required to write these bits were 11.7V and 30V. These devices demonstrated the larger write voltage separation between the bits.

scholarly journals An ISFET Microarray Sensor System for Detecting the DNA Base Pairing

Micromachines ◽  
2021 ◽  
Vol 12 (7) ◽  
pp. 731
Author(s):  
Peng Sun ◽  
Yongxin Cong ◽  
Ming Xu ◽  
Huaqing Si ◽  
Dan Zhao ◽  
...  
Keyword(s):  
Dna Sequencing ◽  
Large Scale ◽  
Ph Value ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Fluorescent Labeling ◽  
Oxide Semiconductor ◽  
Sensor System ◽  
Base Pairing ◽  
Dna Base

Deoxyribonucleic acid (DNA) sequencing technology provides important data for the disclosure of genetic information and plays an important role in gene diagnosis and gene therapy. Conventional sequencing devices are expensive and require large and bulky optical structures and additional fluorescent labeling steps. Sequencing equipment based on a semiconductor chip has the advantages of fast sequencing speed, low cost and small size. The detection of DNA base pairing is the most important step in gene sequencing. In this study, a large-scale ion-sensitive field-effect transistor (ISFET) array chip with more than 13 million sensitive units is successfully designed for detecting the DNA base pairing. DNA base pairing is successfully detected by the sensor system, which includes the ISFET microarray chip, microfluidic system, and test platform. The chip achieves a high resolution of at least 0.5 mV, thus enabling the recognition of the change of 0.01 pH value. This complementary metal-oxide semiconductor (CMOS) compatible and cost-efficient sensor array chip, together with other specially designed components, can form a complete DNA sequencing system with potential application in the molecular biology fields.

Output Voltage Sampling Circuit for Discontinuous Conduction Mode Flyback Pulse-Width Modulation Controller

2016 ◽  
Vol 25 (11) ◽  
pp. 1650140 ◽  
Author(s):  
Ling-Feng Shi ◽  
Zhen-Bo Shi ◽  
Sen Chen ◽  
Jian-Hui Xun
Keyword(s):  
Pulse Width ◽  
Output Voltage ◽  
Pulse Width Modulation ◽  
Low Voltage ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Discharge Time ◽  
Constant Output

Primary-side controlled pulse-width modulation (PWM) flyback converter has been widely used in low-power and low-voltage products for its simple structure and low cost. This paper presents a novel output voltage sampling circuit which considers the influence of the rectifier diode current on the output voltage sampling. The output voltage sampling circuit samples the output voltage at 85% of the secondary inductance discharge time [Formula: see text] of last cycle, which improves the accuracy of the output voltage sampling circuit. Besides, the circuit can also sample the secondary inductance discharge time [Formula: see text]. Finally, a chip has been fabricated in 0.6[Formula: see text][Formula: see text]m complementary metal-oxide semiconductor (CMOS) process, which is used in the presented output voltage sampling circuit in its internal circuit to simple output voltage and achieve constant output voltage.

scholarly journals A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits

Sensors ◽  
2021 ◽  
Vol 21 (13) ◽  
pp. 4462
Author(s):  
Malik Summair Asghar ◽  
Saad Arslan ◽  
HyungWon Kim
Keyword(s):  
Neural Network ◽  
Power Consumption ◽  
Large Scale ◽  
Average Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Input Image ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Spiking Neural Network ◽  
Digital Implementation

To realize a large-scale Spiking Neural Network (SNN) on hardware for mobile applications, area and power optimized electronic circuit design is critical. In this work, an area and power optimized hardware implementation of a large-scale SNN for real time IoT applications is presented. The analog Complementary Metal Oxide Semiconductor (CMOS) implementation incorporates neuron and synaptic circuits optimized for area and power consumption. The asynchronous neuronal circuits implemented benefit from higher energy efficiency and higher sensitivity. The proposed synapse circuit based on Binary Exponential Charge Injector (BECI) saves area and power consumption, and provides design scalability for higher resolutions. The SNN model implemented is optimized for 9 × 9 pixel input image and minimum bit-width weights that can satisfy target accuracy, occupies less area and power consumption. Moreover, the spiking neural network is replicated in full digital implementation for area and power comparisons. The SNN chip integrated from neuron and synapse circuits is capable of pattern recognition. The proposed SNN chip is fabricated using 180 nm CMOS process, which occupies a 3.6 mm2 chip core area, and achieves a classification accuracy of 94.66% for the MNIST dataset. The proposed SNN chip consumes an average power of 1.06 mW—20 times lower than the digital implementation.

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