Output Voltage Sampling Circuit for Discontinuous Conduction Mode Flyback Pulse-Width Modulation Controller

2016 ◽  
Vol 25 (11) ◽  
pp. 1650140 ◽  
Author(s):  
Ling-Feng Shi ◽  
Zhen-Bo Shi ◽  
Sen Chen ◽  
Jian-Hui Xun
Keyword(s):  
Pulse Width ◽  
Output Voltage ◽  
Pulse Width Modulation ◽  
Low Voltage ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Discharge Time ◽  
Constant Output

Primary-side controlled pulse-width modulation (PWM) flyback converter has been widely used in low-power and low-voltage products for its simple structure and low cost. This paper presents a novel output voltage sampling circuit which considers the influence of the rectifier diode current on the output voltage sampling. The output voltage sampling circuit samples the output voltage at 85% of the secondary inductance discharge time [Formula: see text] of last cycle, which improves the accuracy of the output voltage sampling circuit. Besides, the circuit can also sample the secondary inductance discharge time [Formula: see text]. Finally, a chip has been fabricated in 0.6[Formula: see text][Formula: see text]m complementary metal-oxide semiconductor (CMOS) process, which is used in the presented output voltage sampling circuit in its internal circuit to simple output voltage and achieve constant output voltage.

scholarly journals Monolithically-Integrated Single-Photon Avalanche Diode in a Zero-Change Standard CMOS Process for Low-Cost and Low-Voltage LiDAR Application

Instruments ◽  
2019 ◽  
Vol 3 (2) ◽  
pp. 33
Author(s):  
Jinsoo Rhim ◽  
Xiaoge Zeng ◽  
Zhihong Huang ◽  
Sai Rahul Chalamalasetti ◽  
Marco Fiorentino ◽  
...  
Keyword(s):  
Low Voltage ◽  
Single Photon ◽  
Low Cost ◽  
Minimum Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Complete Characterization ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Avalanche Diode ◽  
Monolithically Integrated

We present a single-photon sensor based on the single-photon avalanche diode (SPAD) that is suitable for low-cost and low-voltage light detection and ranging (LiDAR) applications. It is implemented in a zero-change standard 0.18-μm complementary metal oxide semiconductor process at the minimum cost by excluding any additional processing step for customized doping profiles. The SPAD is based on circular shaped P+/N-well junction of 8-μm diameter, and it achieves low breakdown voltage below 10 V so that the operation voltage of the single-photon sensor can be minimized. The quenching and reset circuit is integrated monolithically to capture photon-generated output pulses for measurement. A complete characterization of our single-photon sensor is provided.

scholarly journals A Regulated Temperature-Insensitive High-Voltage Charge Pump in Standard CMOS Process for Micromachined Gyroscopes

Sensors ◽  
2019 ◽  
Vol 19 (19) ◽  
pp. 4149
Author(s):  
Xiang Li ◽  
Rui Li ◽  
Chunge Ju ◽  
Bo Hou ◽  
Qi Wei ◽  
...  
Keyword(s):  
Metal Oxide ◽  
High Voltage ◽  
Output Voltage ◽  
Charge Pump ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Temperature Changes ◽  
Adjustable Range

Micromachined gyroscopes require high voltage (HV) for actuation and detection to improve its precision, but the deviation of the HV caused by temperature fluctuations will degrade the sensor’s performance. In this paper, a high-voltage temperature-insensitive charge pump is proposed. Without adopting BCD (bipolar-CMOS-DMOS) technology, the output voltage can be boosted over the breakdown voltage of n-well/substrate diode using triple-well NMOS (n-type metal-oxide-semiconductor) transistors. By controlling the pumping clock’s amplitude continuously, closed-loop regulation is realized to reduce the output voltage’s sensitivity to temperature changes. Besides, the output level is programmable linearly in a large range by changing the reference voltage. The whole circuit has been fabricated in a 0.18- μ m standard CMOS (complementary metal-oxide-semiconductor) process with a total area of 2.53 mm 2 . Measurements indicate that its output voltage has a linear adjustable range from around 13 V to 16.95 V, and temperature tests show that the maximum variations of the output voltage at − 40 ∼ 80 ∘ C are less than 1.1%.

scholarly journals Research on Modified Hybrid Frequency Modulation Technology of Type-III Asymmetric CHB Multilevel Inverters

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 263
Author(s):  
Manyuan Ye ◽  
Wei Ren ◽  
Qiwen Wei ◽  
Guizhi Song ◽  
Zhilin Miao
Keyword(s):  
Pulse Width ◽  
Output Voltage ◽  
Pulse Width Modulation ◽  
Low Voltage ◽  
Output Line ◽  
Line Voltage ◽  
Multilevel Inverters ◽  
Type Iii ◽  
Hybrid Frequency ◽  
Frequency Pulse

Asymmetric Cascaded H-bridge (ACHB) level inverters can output more voltage waveforms with fewer cascaded units while ensuring the quality of output voltage waveforms, so they have attracted more and more attention. Taking the topology of Type-III asymmetric CHB multilevel inverters as the research object, a Modified Hybrid Frequency Pulse Width Modulation (MHF-PWM) strategy is proposed in this paper. This modulation strategy overcomes the local overshoot of low-voltage unit in the presence of traditional Hybrid Frequency Pulse Width Modulation (HF-PWM), thus completely eliminating the low frequency harmonics in the output voltage waveform of Type-III ACHB nine-level inverters, and the Total Harmonic Distortion (THD) of output line voltage of the modulation strategy is lower than that of PS-PWM strategy in the whole modulation degree, which effectively improves the quality waveform of the output line voltage. At the same time, the strategy can also improve the problems of current backflow and energy feedback caused by the high-voltage unit pouring current to the low-voltage unit, thereby reducing the imbalance of the output power of the high-voltage and low-voltage units. Finally, the Matlab/Simulink simulation model and experimental platform are established to verify the validity and practicality of the modulation strategy.

scholarly journals A Smart Floating Gate Transistor with Two Control Gates for Active Noise Control

Micromachines ◽  
2019 ◽  
Vol 10 (11) ◽  
pp. 722
Author(s):  
Mao ◽  
Yang ◽  
Ma ◽  
Yan ◽  
Zhang
Keyword(s):  
Large Scale ◽  
Noise Control ◽  
Low Cost ◽  
Active Noise Control ◽  
Complementary Metal Oxide Semiconductor ◽  
Floating Gate ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Active Noise ◽  
Floating Gate Transistor

A smart floating gate transistor with two control gates was proposed for active noise control in bioelectrical signal measurement. The device, which is low cost and capable of large-scale integration, was implemented in a standard single-poly complementary metal–oxide–semiconductor (CMOS) process. A model of the device was developed to demonstrate the working principle. Theoretical analysis and simulation results proved the superposition of the two control gates. A series of test experiments were carried out and the results showed that the device was in accordance with the basic electrical characteristics of a floating gate transistor, including the current–voltage (I–V) characteristics and the threshold characteristics observed on the two control gates. Based on the source follower circuit, the experimental results proved that the device can reduce interference by more than 29 dB, which demonstrates the feasibility of the proposed device for active noise control.

Realization of Fractional-Order Double-Scroll Chaotic System Using Operational Transconductance Amplifier (OTA)

2017 ◽  
Vol 27 (01) ◽  
pp. 1850006 ◽  
Author(s):  
Mohammad Rafiq Dar ◽  
Nasir Ali Kant ◽  
Farooq Ahmad Khanday
Keyword(s):  
Fractional Order ◽  
Chaotic System ◽  
Low Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Operational Transconductance Amplifiers ◽  
System A ◽  
Transconductance Amplifier ◽  
Theoretical Predictions

Realization of fractional-order double-scroll chaotic system using Operational Transconductance Amplifiers (OTAs) as active elements are presented in this paper. The fractional-order double-scroll chaotic system has been studied before as well using passive RC-ladder and tree-based structures but in this paper the requisite fractional-order integration has been accomplished through an integer-order multiple-feedback topology. As compared to double or multiple scroll chaotic systems existing in the open literature, the proposed realization offers the advantages of (a) low-voltage implementation, (b) integrablity as the design is resistor- and inductor-less and only grounded components have been employed in the design, and, (c) electronic tunability of the fractional order, time-constants and gain factors. In order to demonstrate the usefulness of the chaotic system, a simple secure message communication system has been designed and verified for its operation. The theoretical predictions of the proposed implementations have been verified by using 0.35[Formula: see text][Formula: see text]m complementary metal oxide semiconductor (CMOS) process file provided by Austrian Micro System (AMS).

scholarly journals A Fully-Integrated 180 nm CMOS 1.2 V Low-Dropout Regulator for Low-Power Portable Applications

Electronics ◽  
2021 ◽  
Vol 10 (17) ◽  
pp. 2108
Author(s):  
Jorge Pérez-Bailón ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Low Voltage ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
High Gain ◽  
Oxide Semiconductor ◽  
Fully Integrated ◽  
Low Voltage Operation ◽  
Error Amplifier ◽  
Ldo Regulator

This paper presents the design and postlayout simulation results of a capacitor-less low dropout (LDO) regulator fully integrated in a low-cost standard 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology which regulates the output voltage at 1.2 V from a 3.3 to 1.3 V battery over a –40 to 120°C temperature range. To meet with the constraints of system-on-chip (SoC) battery-operated devices, ultralow power (Iq = 8.6 µA) and minimum area consumption (0.109 mm2) are maintained, including a reference voltage Vref = 0.4 V. It uses a high-gain dynamically biased folded-based error amplifier topology optimized for low-voltage operation that achieves an enhanced regulation-fast transient performance trade-off.

scholarly journals Analysis of a DC Converter with Low Primary Current Loss and Balance Voltage and Current

Electronics ◽  
2019 ◽  
Vol 8 (4) ◽  
pp. 439 ◽  
Author(s):  
Lin
Keyword(s):  
Pulse Width ◽  
Pulse Width Modulation ◽  
Low Voltage ◽  
Field Effect Transistors ◽  
Magnetic Coupling ◽  
Oxide Semiconductor ◽  
Current Loss ◽  
Control Approach ◽  
Switching Characteristics ◽  
Primary Current

A dc/dc pulse width modulation (PWM) circuit was investigated to realize the functions of reduced primary current loss and balanced voltage and current distribution. In the presented dc/dc converter, two full bridge pulse width modulation circuits were used with the series/parallel connection on the high-voltage/low-voltage side. The flying capacitor was adopted on the input side to achieve voltage balance on input split capacitors. The magnetic coupling element was employed to achieve current sharing between two parallel circuits. A capacitor-diode passive circuit was adopted to lessen the primary current at the commutated interval. The phase-shifted duty cycle control approach was employed to regulate load voltage and implement soft switching characteristics of power metal-oxide-semiconductor field-effect transistors (MOSFETs). Finally, the experimental results using a 1.68 kW prototype converter were obtained to confirm the performance and feasibility of the studied circuit topology.

Design of Clock and Ramp Generator Circuit Framework with 0.9V Low Operational Voltage

2013 ◽  
Vol 284-287 ◽  
pp. 2502-2508
Author(s):  
Rong Jong Wai ◽  
Jun Jie Liaw
Keyword(s):  
Threshold Voltage ◽  
Pulse Width Modulation ◽  
Low Voltage ◽  
Clean Energy ◽  
Oxide Semiconductor ◽  
Operational Amplifiers ◽  
Cmos Process ◽  
Clock Frequency ◽  
Ramp Generator ◽  
Generator Circuit

In this study, a new clock and ramp generator circuit framework with a 0.9V low operational voltage is designed for the voltage-mode/current-mode-controlled power management integrated chip of a DC-DC converter. In conventional clock and ramp generator circuit with operational amplifiers, its operational voltage is limited to be over 1.5V because of the problem of a higher threshold voltage in the metal-oxide-semiconductor field-effect transistor (MOSFET). As a result, it can not work well for a pulse-width-modulation DC-DC converter when a below 1V low-voltage single-cell clean-energy power source is applied. This newly-design clock and ramp generator circuit framework without operational amplifiers is investigated to cope with the limitation of the threshold voltage in the MOSFET. Therefore, the corresponding chip size and power consumption can be reduced. Moreover, this circuit still has the functions of adjustable clock frequency and ramp slope. In addition, numerical simulations by the HSPICE software and experimental results by a real chip fabricated in the TSMC 1P6M 0.18µm CMOS process are given to verify the effectiveness of the proposed circuit to produce the clock and ramp waveforms.

scholarly journals Low-Cost Microbolometer Type Infrared Detectors

Micromachines ◽  
2020 ◽  
Vol 11 (9) ◽  
pp. 800
Author(s):  
Le Yu ◽  
Yaozu Guo ◽  
Haoyu Zhu ◽  
Mingcheng Luo ◽  
Ping Han ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Focal Plane ◽  
Technological Development ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Micro Electro Mechanical System ◽  
Focal Plane Arrays ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Cmos Compatible

The complementary metal oxide semiconductor (CMOS) microbolometer technology provides a low-cost approach for the long-wave infrared (LWIR) imaging applications. The fabrication of the CMOS-compatible microbolometer infrared focal plane arrays (IRFPAs) is based on the combination of the standard CMOS process and simple post-CMOS micro-electro-mechanical system (MEMS) process. With the technological development, the performance of the commercialized CMOS-compatible microbolometers shows only a small gap with that of the mainstream ones. This paper reviews the basics and recent advances of the CMOS-compatible microbolometer IRFPAs in the aspects of the pixel structure, the read-out integrated circuit (ROIC), the focal plane array, and the vacuum packaging.

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