scholarly journals A Low-Resources TDC for Multi-Channel Direct ToF Readout Based on a 28-nm FPGA

Sensors ◽  
2021 ◽  
Vol 21 (1) ◽  
pp. 308
Author(s):  
Mojtaba Parsakordasiabi ◽  
Ion Vornicu ◽  
Ángel Rodríguez-Vázquez ◽  
Ricardo Carmona-Galán
Keyword(s):  
Field Programmable Gate Array ◽  
High Performance ◽  
Delay Line ◽  
Time Of Flight ◽  
Experimental Results ◽  
Digital Converter ◽  
Input Stage ◽  
Online Calibration ◽  
Field Programmable ◽  
Gate Array

In this paper, we present a proposed field programmable gate array (FPGA)-based time-to-digital converter (TDC) architecture to achieve high performance with low usage of resources. This TDC can be employed for multi-channel direct Time-of-Flight (ToF) applications. The proposed architecture consists of a synchronizing input stage, a tuned tapped delay line (TDL), a combinatory encoder of ones and zeros counters, and an online calibration stage. The experimental results of the TDC in an Artix-7 FPGA show a differential non-linearity (DNL) in the range of [−0.953, 1.185] LSB, and an integral non-linearity (INL) within [−2.750, 1.238] LSB. The measured LSB size and precision are 22.2 ps and 26.04 ps, respectively. Moreover, the proposed architecture requires low FPGA resources.

scholarly journals Experimental Investigation on the Performances of a Multilevel Inverter Using a Field Programmable Gate Array-Based Control System

Energies ◽  
2019 ◽  
Vol 12 (6) ◽  
pp. 1016 ◽  
Author(s):  
Guido Ala ◽  
Massimo Caruso ◽  
Rosario Miceli ◽  
Filippo Pellitteri ◽  
Giuseppe Schettino ◽  
...  
Keyword(s):  
Experimental Investigation ◽  
Field Programmable Gate Array ◽  
High Performance ◽  
Multilevel Inverter ◽  
Experimental Results ◽  
Digital Controllers ◽  
Field Programmable ◽  
Gate Array ◽  
High Flexibility ◽  
Valid Solution

The Field Programmable Gate Array (FPGA) represents a valid solution for the design of control systems for inverters adopted in many industry applications, because of both its high flexibility of use and its high-performance with respect to other types of digital controllers. In this context, this paper presents an experimental investigation on the harmonic content of the voltages produced by a three-phase, five level cascaded H-Bridge Multilevel inverter with an FPGA-based control board, aiming also to evaluate the performance of the FPGA through the implementation of the main common modulation techniques and the comparison between simulation and experimental results. The control algorithms are implemented by means of the VHDL programming language. The output voltage waveforms, which have been obtained by applying to the inverter the main PWM techniques, are compared in terms of THD%. Simulation and experimental results are analyzed, compared and finally discussed.

scholarly journals Implementation of sub-nanosecond time-to-digital convertor in field-programmable gate array: applications to time-of-flight analysis in muon radiography

2014 ◽  
Vol 25 (3) ◽  
pp. 035101 ◽  
Author(s):  
Jacques Marteau ◽  
Jean de Bremond d’Ars ◽  
Dominique Gibert ◽  
Kevin Jourde ◽  
Serge Gardien ◽  
...  
Keyword(s):  
Field Programmable Gate Array ◽  
Time Of Flight ◽  
Muon Radiography ◽  
Field Programmable ◽  
Gate Array

scholarly journals Enabling Packet Classification with Low Update Latency for SDN Switch on FPGA

2020 ◽  
Vol 12 (8) ◽  
pp. 3068 ◽  
Author(s):  
Chenglong Li ◽  
Tao Li ◽  
Junnan Li ◽  
Zilin Shi ◽  
Baosheng Wang
Keyword(s):  
Real Time ◽  
Field Programmable Gate Array ◽  
High Performance ◽  
Recursive Algorithm ◽  
Packet Classification ◽  
Experimental Results ◽  
The Core ◽  
Core Function ◽  
Field Programmable ◽  
Bit Vector

Field Programmable Gate Array (FPGA) is widely used in real-time network processing such as Software-Defined Networking (SDN) switch due to high performance and programmability. Bit-Vector (BV)-based approaches can implement high-performance multi-field packet classification, on FPGA, which is the core function of the SDN switch. However, the SDN switch requires not only high performance but also low update latency to avoid controller failure. Unfortunately, the update latency of BV-based approaches is inversely proportional to the number of rules, which means can hardly support the SDN switch effectively. It is reasonable to split the ruleset into sub-rulesets that can be performed in parallel, thereby reducing update latency. We thus present SplitBV for the efficient update by using several distinguishable exact-bits to split the ruleset. SplitBV consists of a constrained recursive algorithm for selecting the bit positions that can minimize the latency and a hybrid lookup pipeline. It can achieve a significant reduction in update latency with negligible memory growth and comparable high performance. We implement SplitBV and evaluate its performance by simulation and FPGA prototype. Experimental results show that our approach can reduce 73% and 36% update latency on average for synthetic 5-tuple rules and OpenFlow rules respectively.

Sign in / Sign up

Export Citation Format

Share Document