scholarly journals An Area Efficient Wallace Tree Multiplier using Modified Full Adder

2020 ◽  
Vol 8 (6) ◽  
pp. 3383-3386
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Digital Signal ◽  
Full Adder ◽  
Nand Gate ◽  
Silicon Area ◽  
Wallace Tree ◽  
Multiplication Process ◽  
Wallace Tree Multiplier ◽  
Area Efficient

Multipliers play a significant task in digital signal processing applications and application-specific integrated circuits. Wallace tree multipliers provide a high-speed multiplication process with an area-efficient strategy. It is realized in hardware using full adders and half adders. The optimization of adders can further improve the performance of multipliers. Wallace tree multiplier with modified full adder using NAND gate is proposed to achieve reduced silicon area, high speed and low power consumption. The conventional full adder implemented by XOR, AND, OR gates is replaced by the modified full adder realized using NAND gate. The proposed Wallace tree multiplier includes 544 transistors, while the conventional Wallace tree multiplier has 584 transistors for 4-bit multiplication.

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

Design of area-efficient high speed 4 × 4 Wallace tree multiplier using quantum-dot cellular automata

2020 ◽  
Author(s):  
A. Arunkumar Gudivada ◽  
K. Jayaram Kumar ◽  
Srinivasa Rao Jajula ◽  
Durga Prasad Siddani ◽  
Praveen Kumar Poola ◽  
...  
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
High Speed ◽  
Quantum Dot Cellular Automata ◽  
Wallace Tree ◽  
Wallace Tree Multiplier ◽  
Area Efficient

scholarly journals Optimization of Arithmetical Operators for the Enhanced Wallace Stage

2018 ◽  
Vol 9 (3) ◽  
pp. 591
Author(s):  
K. Gugan ◽  
S. V. Saravanan
Keyword(s):  
Signal Processing ◽  
Digital Signal ◽  
Full Adder ◽  
Fir Filter ◽  
Digital Form ◽  
Multiplication Process ◽  
Initial Stage ◽  
Direct Form ◽  
Two Stages ◽  
Wallace Tree Multiplier

<p>In the field of Digital signal processing (DSP), the reduction of some logical elements counts is one of the main considerations. To minimize the area, computational delay, and power, the digital form FIR filter is to be implemented. The optimization of the ATP (Area, Time and Power) is achieved by using the efficient multiplication and accumulation unit (MAC). In this work, the direct form FIR filter with the efficient MAC unit is presented. At the initial stage, the half adders and full adders are to be modified by the reduction of the logical gates. The modified half and full adder are implemented in the Wallace tree multiplier for performing the efficient multiplication process. Carry save adder is divided into the two stages to reduce the computational delay of arithmetical operators. The proposed MAC design is implemented in the direct form FIR filter by using the HDL language.</p>

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