An Efficient Algorithm for Fast Block Motion Estimation in High Efficiency Video Coding

Author(s):  
Murugesan Ezhilarasan ◽  
Kumar K. Nirmal ◽  
P. Thambidurai

The Motion Estimation is an indispensable module in the design of video encoder. It employs Block Matching algorithm which involves searching a candidate block in the entire search window of the reference frame taking up to 80% of the total video encoding time. In order to increase the efficiency, several Block Matching Algorithms are employed to minimize the computational time involved in block matching. The chapter throws light on an efficient approach to be applied to the existing Block Matching Search techniques in HEVC which outperforms the various Block Matching algorithms. It involves two steps namely – Prediction and Refinement. The prediction step considers two parameters such as the temporal correlation and the direction to predict the MV of the candidate block. Several combinations of the search points are formulated in the refinement step of the algorithm to minimize the search time. The results depict that the Efficient Motion Estimation schemes provide a faster search minimizing the computational time upon comparison with the existing Motion Estimation algorithms.

2021 ◽  
Author(s):  
Randa Khemiri ◽  
Soulef Bouaafia ◽  
Asma Bahba ◽  
Maha Nasr ◽  
Fatma Ezahra Sayadi

In Motion estimation (ME), the block matching algorithms have a great potential of parallelism. This process of the best match is performed by computing the similarity for each block position inside the search area, using a similarity metric, such as Sum of Absolute Differences (SAD). It is used in the various steps of motion estimation algorithms. Moreover, it can be parallelized using Graphics Processing Unit (GPU) since the computation algorithm of each block pixels is similar, thus offering better results. In this work a fixed OpenCL code was performed firstly on several architectures as CPU and GPU, secondly a parallel GPU-implementation was proposed with CUDA and OpenCL for the SAD process using block of sizes from 4x4 to 64x64. A comparative study established between execution time on GPU on the same video sequence. The experimental results indicated that GPU OpenCL execution time was better than that of CUDA times with performance ratio that reached the double.


2018 ◽  
Vol 8 (1) ◽  
pp. 38-56 ◽  
Author(s):  
Shailesh D. Kamble ◽  
Sonam T. Khawase ◽  
Nileshsingh V. Thakur ◽  
Akshay V. Patharkar

Motion estimation has traditionally been used in video encoding only, however, it can also be used to solve various real-life problems. Nowadays, researchers from different fields are turning towards motion estimation. Motion estimation has become a serious problem in many video applications. It is a very important part of video compression technique and it provides improved bit rate reduction and coding efficiency. The process of motion estimation is used to improve compression quality and it also reduces computation time. Block-based motion estimation algorithms are used as they require less memory for processing of any video file. It also reduces the complexity involved in computations. In this article, various block-matching motion estimation algorithms are discussed such as Full search (FS) or Exhaust Search, Three-Step search (TSS), New Three-Step search (NTSS), Four-Step search (FSS), Diamond search (DS) etc.


Video compression is a very complex and time consuming task which generally pursuit high performance. Motion Estimation (ME) process in any video encoder is responsible to primarily achieve the colossal performance which contributes to significant compression gain. Summation of Absolute Difference (SAD) is widely applied as distortion metric for ME process. With the increase in block size to 64×64 for real time applications along with the introduction of asymmetric mode motion partitioning(AMP) in High Efficiency Video Encoding (HEVC)causes variable block size motion estimation very convoluted. This results in increase in computational time and demands for significant requirement of hardware resources. In this paper parallel SAD hardware circuit for ME process in HEVC is propound where parallelism is used at various levels. The propound circuit has been implemented using Xilinx Virtex-5 FPGA for XC5VLX20T family. Synthesis results shows that the propound circuit provides significant reduction in delay and increase in frequency in comparison with results of other parallel architectures.


Author(s):  
A.V. Paramkusam ◽  
D. Laxma Reddy

<p>This paper proposes compact directional asymmetric search patterns, which we have named as three-point directional search (TDS). In most fast search motion estimation algorithms, a symmetric search pattern is usually set at the minimum block distortion point at each step of the search. The design of the symmetrical pattern in these algorithms relies primarily on the assumption that the direction of convergence is equally alike in each direction with respect to the search center. Therefore, the monotonic property of real-world video sequences is not properly used by these algorithms. The strategy of TDS is to keep searching for the minimum block distortion point in the most probable directions, unlike the previous fast search motion estimation algorithms where all the directions are checked. Therefore, the proposed method significantly reduces the number of search points for locating a motion vector. Compared to conventional fast algorithms, the proposed method has the fastest search speed and most satisfactory PSNR values for all test sequences.</p>


Sensors ◽  
2019 ◽  
Vol 19 (4) ◽  
pp. 895 ◽  
Author(s):  
Seung-Yong Lee ◽  
Chae Rhee

Noise, which is commonly generated in low-light environments or by low-performance cameras, is a major cause of the degradation of compression efficiency. In previous studies that attempted to combine a denoise algorithm and a video encoder, denoising was used independently of the code for pre-processing or post-processing. However, this process must be tightly coupled with encoding because noise affects the compression efficiency greatly. In addition, this represents a major opportunity to reduce the computational complexity, because the encoding process and a denoise algorithm have many similarities. In this paper, a simple, add-on denoising scheme is proposed through a combination of high-efficiency video coding (HEVC) and block matching three-dimensional collaborative filtering (BM3D) algorithms. It is known that BM3D has excellent denoise performance but that it is limited in its use due to its high computational complexity. This paper employs motion estimation in HEVC to replace the block matching of BM3D so that most of the time-consuming functions are shared. To overcome the challenging algorithmic differences, the hierarchical structure in HEVC is uniquely utilized. As a result, the computational complexity is drastically reduced while the competitive performance capabilities in terms of coding efficiency and denoising quality are maintained.


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