Multi-Standard Multi-Band Reconfigurable LNA

2012 ◽  
pp. 1-23
Author(s):  
Mohd Tafir Mustaffa
Keyword(s):  
Mobile Communication ◽  
Cmos Technology ◽  
Low Noise ◽  
Good Choice ◽  
Common Source ◽  
Lower Band ◽  
Noise Amplifier ◽  
Mobile Receiver ◽  
Reconfigurable Lna ◽  
Multi Band

In this research, the aim is to design and implement a new low noise amplifier (LNA) for a multi-standard mobile receiver based on reconfigurability concept. The LNA design is based on the inductively-degenerated common-source (IDCS) topology as it has been proven to be a good choice in designing multi-standard multi-band LNA. The design is using 0.18 µm CMOS technology. The reconfigurable LNA has been designed to operate in two bands of standards consisting the bands range from 800 to 1000-MHz (lower band) and 1800 to 2200-MHz (upper band). The simulation results exhibit gain S21 of 12.9-dB for lower band and 12.4-dB for upper band, input reflection S11 of -14.5-dB and -17.2-dB for both bands, and output return loss S22 of -14.7-dB and -26-dB for lower and upper band making the LNA suitable for most of the mobile communication applications. The LNA also exhibits the noise of figure of 2.55-dB and 2.3-dB for lower and upper band respectively. The circuit consumes 26.5 mW when operating in lower band mode and uses 18.8 mW of power when operating in upper band mode.

Inductive Feedback Technique for Design of High Gain 0.18μm CMOS LNA for 5G Applications

2021 ◽  
pp. 2150236
Author(s):  
Anjana Jyothi Banu ◽  
G. Kavya ◽  
D. Jahnavi
Keyword(s):  
Reflection Coefficient ◽  
Noise Figure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Common Source ◽  
Matching Network ◽  
Input Matching ◽  
Cmos Lna ◽  
Noise Amplifier

A 26[Formula: see text]GHz low-noise amplifier (LNA) designed for 5G applications using 0.18[Formula: see text][Formula: see text]m CMOS technology is proposed in this paper. The circuit includes a common-source in the first stage to suppress the noise in the amplifier. The successive stage has a Cascode topology along with an inductive feedback to improve the power gain. The input matching network is designed to achieve the input reflection coefficient less than [Formula: see text]7dB at the intended frequency. The matching network at the output is designed using inductor–capacitor (LC) components connected in parallel to attain the output reflection coefficient of [Formula: see text]10[Formula: see text]dB. Due to the inductor added in feedback at the second stage. The [Formula: see text] obtained is 18.208[Formula: see text]dB at 26[Formula: see text]GHz with a noise figure (NF) of 2.8[Formula: see text]dB. The power supply given to the LNA is 1.8[Formula: see text]V. The simulation and layout of the presented circuit are performed using Cadence Virtuoso software.

scholarly journals Design And Analysis Of CMOS Low Noise Amplifier Circuit For 5-GHz Cascode and Folded Cascode In 180nm Technology

2018 ◽  
Vol 7 (3) ◽  
pp. 143
Author(s):  
T. Kanthi ◽  
D. Sharath Babu Rao
Keyword(s):  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Source ◽  
Power Gain ◽  
Amplifier Circuit ◽  
Folded Cascode ◽  
Noise Amplifier ◽  
5 Ghz

This paper is about Low noise amplifier topologies based on 0.18µm CMOS technology. A common source stage with inductive degeneration, cascode stage and folded cascode stage is designed, simulated and the performance has been analyzed. The LNA’s are designed in 5GHz. The LNA of cascode stage of noise figure (NF) 2.044dB and power gain 4.347 is achieved. The simulations are done in cadence virtuoso spectre RF.

scholarly journals Design And Analysis Of CMOS Low Noise Amplifier Circuit For 5-GHz Cascode and Folded Cascode In 180nm Technology

2018 ◽  
Vol 7 (3) ◽  
pp. 149
Author(s):  
T. Kanthi ◽  
D. Sharath Babu Rao
Keyword(s):  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Source ◽  
Power Gain ◽  
Amplifier Circuit ◽  
Folded Cascode ◽  
Noise Amplifier ◽  
5 Ghz

This paper is about Low noise amplifier topologies based on 0.18µm CMOS technology. A common source stage with inductive degeneration, cascode stage and folded cascode stage is designed, simulated and the performance has been analyzed. The LNA’s are designed in 5GHz. The LNA of cascode stage of noise figure (NF) 2.044dB and power gain 4.347 is achieved. The simulations are done in cadence virtuoso spectre RF.

scholarly journals Design and Implementation of Low Noise Amplifier At 60ghz using Current Mirror Feedback

2019 ◽  
Vol 8 (9S3) ◽  
pp. 249-254
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Single Stage ◽  
Common Source ◽  
Small Signal ◽  
Total Size ◽  
Noise Amplifier

This discourse used 45nm CMOS technology to design a Low noise amplifier for a Noise figure < 2dB and gain greater than 13dB at the 60GHz unlicensed band of frequency. A single stage, primary cascode LNA is modeled and its small signal model is analyzed. Common source structure is hired in the driver stage to escalate the output power with single stage contours. To enhance small signal gain, simple active transistor feedback and cascode feedback configurations are designed and appended to the basic LNA. In addition to this, current re-use inductor is designed and added to the cascode amplifier which is deliberated to give low power and low noise figure. Small signal analysis of simple active transistor feedback and current re-use inductor has been presented. The measurement results indicated that the input match and the output gain at 60GHz achieves -8dB and 13dB respectively with the supply voltage of 900mV. The frequency response obtained is a narrow band response with 6GHz of bandwidth. The circuit is simulated by Cadence Virtuoso tool. The layout of the related circuit is drawn by means of the Virtuoso Layout editor with total size of 0.1699μm2.

A V-Band Common-Source Low Noise Amplifier in a 0.13µm RF CMOS Technology and the Effect of Dummy Fills

2011 ◽  
Vol E94-C (5) ◽  
pp. 807-813 ◽  
Author(s):  
Sungjin KIM ◽  
Hyunchul KIM ◽  
Dong-Hyun KIM ◽  
Sanggeun JEON ◽  
Yeocho YOON ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Source ◽  
Rf Cmos ◽  
V Band ◽  
Noise Amplifier

A Single-To-Differential LNA using Differential Active Inductor for GPS Applications

Frequenz ◽  
2013 ◽  
Vol 67 (1-2) ◽  
Author(s):  
Hojjat Babaei Kia ◽  
Abu Khari A'ain
Keyword(s):  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Source ◽  
Active Inductor ◽  
Active Load ◽  
Common Gate ◽  
Noise Amplifier ◽  
On Chip

AbstractThis paper presents the design of a single-ended input, differential output low noise amplifier for GPS applications in 0.18 µm CMOS technology. This Low Noise Amplifier (LNA) is composed of a common source (CS) amplifier adopted with a common gate, common source (CGCS) balun load. Instead of spiral on-chip inductor, a differential active inductor circuit (DAI) is used as an active load of balun and also

scholarly journals A concurrent dual-band CMOS low noise amplifier at 2.4/5.2 GHz for WLAN applications

2019 ◽  
Vol 14 (2) ◽  
pp. 555
Author(s):  
S.A.Z. Murad ◽  
A. F. Hasan ◽  
A. Azizan ◽  
A. Harun ◽  
J. Karim
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Notch Filter ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Dual Band ◽  
Common Source ◽  
Noise Amplifier

<span>This paper presents a concurrent dual-band CMOS low noise amplifier (LNA) at operating frequency of 2.4 GHz and 5.2 GHz for WLAN applications. The proposed LNA employed cascode common source to obtain high gain using 0.13-µm CMOS technology. The concurrent dual-band frequencies are matched using LC network band-pass and band-stop notch filter at the input and output stages. The filters help to shape the frequency response of the proposed LNA. The simulation results indicate that the LNA achieves a forward gain of 21.8 dB and 14.22 dB, input return loss of -18 dB and -14 dB at 2.4 GHz and 5.2 GHz, respectively. The noise figure of 4.1 dB and 3.5 dB with the input third-order intercept points 7 dBm and 10 dBm are obtained at 2.4 GHz and 5.2 GHz, respectively. The LNA dissipates 2.4 mW power at 1.2 V supply voltage with a chip size of 1.69 mm2.</span>

scholarly journals Low Noise Amplifier with Improved Gain and Reduced Noise-Figure in 90nm CMOS Technology

2021 ◽  
pp. 85-94
Author(s):  
Dr. Rashmi S B ◽  
Mr. Raghavendra B ◽  
Mr. Sanketh V
Keyword(s):  
Reflection Coefficient ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Common Source ◽  
Frequency Range ◽  
Common Gate ◽  
Noise Amplifier

A CMOS low noise amplifier (LNA) for ultra-wideband (UWB) wireless applications is presented in this paper. The proposed CMOS low noise amplifier (LNA) is designed using common-gate (CG) topology as the first stage to achieve ultra-wideband input matching. The common-gate (CG) is cascaded with common- source (CS) topology with current-reused configuration to enhance the gain and noise figure (NF) performance of the LNA with low power. The Buffer stage is used as output matching network to improve the reflection coefficient. The proposed low noise amplifier (LNA) is implemented using CADENCE Virtuoso Analog and Digital Design Environment tool in 90nm CMOS technology. The LNA provides a forward voltage gain or power gain (S21) of 32.34dB , a minimum noise figure of 2dB, a reverse-isolation (S12) of less than - 38.74dB and an output reflection coefficient (S22) of less than -7.4dB for the entire ultra-wideband frequency range. The proposed LNA has an input reflection coefficient (S11) of less than -10dB for the ultra-wideband frequency range. It achieves input referred 1-dB compression point of 78.53dBm and input referred 3-dB compression point of 13dBm. It consumes only 24.226mW of power from a Vdd supply of 0.7V.

A switchable dual‐mode fully‐differential common‐source low‐noise amplifier in 0.18‐μm CMOS technology

2019 ◽  
Vol 62 (3) ◽  
pp. 1163-1168
Author(s):  
Changchun Zhang ◽  
Yongkai Wang ◽  
Shenjun Gao ◽  
Lu Tang ◽  
Yi Zhang ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Source ◽  
Dual Mode ◽  
Fully Differential ◽  
Noise Amplifier

A 79GHz Adaptive Gain Low Noise Amplifier for Radar Receivers

2018 ◽  
Vol 7 (2.24) ◽  
pp. 227
Author(s):  
J Manjula ◽  
A Ruhan Bevi
Keyword(s):  
Reflection Coefficient ◽  
Noise Figure ◽  
Cmos Technology ◽  
Input Power ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Center Frequency ◽  
Common Source ◽  
Adaptive Biasing ◽  
Noise Amplifier

This paper presents an Adaptive Gain 79GHz Low Noise Amplifier (LNA) suitable for Radars applications. The circuit schematic is a two stage LNA consists of Differential cascode configuration followed by a simple common source amplifier with an Adaptive Biasing (ADB) circuit. Adaptive biasing is a three- stage common source amplifier to decrease output voltage as input power increases. The circuit is simulated in 180nm CMOS technology and the simulation results have proved that the circuit operates at the center frequency 79GHz with adaptive biasing for adaptive gain. The gain analysis shows a decrease of 35-30dB with an increase in input power -50 to 0 dB. At 79GHz the circuit has achieved the input reflection coefficient (S11) of -24.7dB, reverse isolation (S12) of -3 dB, forward transmission coefficient (S21) of -2.97dB and output reflection coefficient (S22) of -5.62 dB with the reduced noise figure of 0.9 dB and a power consumption of 236 mW.  

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