scholarly journals A concurrent dual-band CMOS low noise amplifier at 2.4/5.2 GHz for WLAN applications

2019 ◽  
Vol 14 (2) ◽  
pp. 555
Author(s):  
S.A.Z. Murad ◽  
A. F. Hasan ◽  
A. Azizan ◽  
A. Harun ◽  
J. Karim
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Notch Filter ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Dual Band ◽  
Common Source ◽  
Noise Amplifier

<span>This paper presents a concurrent dual-band CMOS low noise amplifier (LNA) at operating frequency of 2.4 GHz and 5.2 GHz for WLAN applications. The proposed LNA employed cascode common source to obtain high gain using 0.13-µm CMOS technology. The concurrent dual-band frequencies are matched using LC network band-pass and band-stop notch filter at the input and output stages. The filters help to shape the frequency response of the proposed LNA. The simulation results indicate that the LNA achieves a forward gain of 21.8 dB and 14.22 dB, input return loss of -18 dB and -14 dB at 2.4 GHz and 5.2 GHz, respectively. The noise figure of 4.1 dB and 3.5 dB with the input third-order intercept points 7 dBm and 10 dBm are obtained at 2.4 GHz and 5.2 GHz, respectively. The LNA dissipates 2.4 mW power at 1.2 V supply voltage with a chip size of 1.69 mm2.</span>

scholarly journals Design and Implementation of Low Noise Amplifier At 60ghz using Current Mirror Feedback

2019 ◽  
Vol 8 (9S3) ◽  
pp. 249-254
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Single Stage ◽  
Common Source ◽  
Small Signal ◽  
Total Size ◽  
Noise Amplifier

This discourse used 45nm CMOS technology to design a Low noise amplifier for a Noise figure < 2dB and gain greater than 13dB at the 60GHz unlicensed band of frequency. A single stage, primary cascode LNA is modeled and its small signal model is analyzed. Common source structure is hired in the driver stage to escalate the output power with single stage contours. To enhance small signal gain, simple active transistor feedback and cascode feedback configurations are designed and appended to the basic LNA. In addition to this, current re-use inductor is designed and added to the cascode amplifier which is deliberated to give low power and low noise figure. Small signal analysis of simple active transistor feedback and current re-use inductor has been presented. The measurement results indicated that the input match and the output gain at 60GHz achieves -8dB and 13dB respectively with the supply voltage of 900mV. The frequency response obtained is a narrow band response with 6GHz of bandwidth. The circuit is simulated by Cadence Virtuoso tool. The layout of the related circuit is drawn by means of the Virtuoso Layout editor with total size of 0.1699μm2.

scholarly journals Linearity improvement of differential CMOS low noise amplifier

2019 ◽  
Vol 14 (1) ◽  
pp. 407
Author(s):  
Maizan Muhamad ◽  
Norhayati Soin ◽  
Harikrishnan Ramiah
Keyword(s):  
Integrated Circuit ◽  
Wireless Lan ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Source ◽  
Linearity Improvement ◽  
Noise Amplifier

<p>This paper presents the linearity improvement of differential CMOS low noise amplifier integrated circuit using 0.13um CMOS technology. In this study, inductively degenerated common source topology is adopted for wireless LAN application. The linearity of the single-ended LNA was improved by using differential structures with optimum biasing technique. This technique achieved better LNA and linearity performance compare with single-ended structure. Simulation was made by using the cadence spectre RF tool. Consuming 5.8mA current at 1.2V supply voltage, the designed LNA exhibits S<sub>21</sub> gain of 18.56 dB, noise figure (NF) of 1.85 dB, S<sub>11</sub> of −27.63 dB, S<sub>22</sub> of -34.33 dB, S<sub>12</sub> of −37.09 dB and IIP3 of -7.79 dBm.</p>

Inductive Feedback Technique for Design of High Gain 0.18μm CMOS LNA for 5G Applications

2021 ◽  
pp. 2150236
Author(s):  
Anjana Jyothi Banu ◽  
G. Kavya ◽  
D. Jahnavi
Keyword(s):  
Reflection Coefficient ◽  
Noise Figure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Common Source ◽  
Matching Network ◽  
Input Matching ◽  
Cmos Lna ◽  
Noise Amplifier

A 26[Formula: see text]GHz low-noise amplifier (LNA) designed for 5G applications using 0.18[Formula: see text][Formula: see text]m CMOS technology is proposed in this paper. The circuit includes a common-source in the first stage to suppress the noise in the amplifier. The successive stage has a Cascode topology along with an inductive feedback to improve the power gain. The input matching network is designed to achieve the input reflection coefficient less than [Formula: see text]7dB at the intended frequency. The matching network at the output is designed using inductor–capacitor (LC) components connected in parallel to attain the output reflection coefficient of [Formula: see text]10[Formula: see text]dB. Due to the inductor added in feedback at the second stage. The [Formula: see text] obtained is 18.208[Formula: see text]dB at 26[Formula: see text]GHz with a noise figure (NF) of 2.8[Formula: see text]dB. The power supply given to the LNA is 1.8[Formula: see text]V. The simulation and layout of the presented circuit are performed using Cadence Virtuoso software.

scholarly journals Design And Analysis Of CMOS Low Noise Amplifier Circuit For 5-GHz Cascode and Folded Cascode In 180nm Technology

2018 ◽  
Vol 7 (3) ◽  
pp. 143
Author(s):  
T. Kanthi ◽  
D. Sharath Babu Rao
Keyword(s):  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Source ◽  
Power Gain ◽  
Amplifier Circuit ◽  
Folded Cascode ◽  
Noise Amplifier ◽  
5 Ghz

This paper is about Low noise amplifier topologies based on 0.18µm CMOS technology. A common source stage with inductive degeneration, cascode stage and folded cascode stage is designed, simulated and the performance has been analyzed. The LNA’s are designed in 5GHz. The LNA of cascode stage of noise figure (NF) 2.044dB and power gain 4.347 is achieved. The simulations are done in cadence virtuoso spectre RF.

scholarly journals Single Stage 180nm CMOS Low Noise Amplifier Topologies and Optimization Algorithms for S Band Frequency

2019 ◽  
Vol 8 (3) ◽  
pp. 152-157 ◽  
Keyword(s):  
Noise Figure ◽  
Optimization Algorithms ◽  
Satellite System ◽  
High Gain ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Dual Band ◽  
Active Device ◽  
Band Frequency ◽  
Noise Amplifier

Low Noise Amplifier (LNA) plays an important role in radio receivers. It mainly determines the system noise and intermodulation behavior of overall receiver. LNA design is more challenging as it requires high gain, low noise figure, good input and output matching and unconditional stability. Further, designing a Low noise Amplifier requires active device selection, amplifier topology, optimization algorithms for superlative results. Hence this paper presents performance analysis of CMOS LNA based on different topologies and optimization algorithms for 180nm RF CMOS design in S band frequency. Here the best results, various limitations in each topology are reviewed and required specifications are determined in each designing. Further this best topology is used for designing LNA circuit which could be used in Indian Regional Navigation Satellite System (IRNSS) applications in dual band frequency.

scholarly journals Design And Analysis Of CMOS Low Noise Amplifier Circuit For 5-GHz Cascode and Folded Cascode In 180nm Technology

2018 ◽  
Vol 7 (3) ◽  
pp. 149
Author(s):  
T. Kanthi ◽  
D. Sharath Babu Rao
Keyword(s):  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Source ◽  
Power Gain ◽  
Amplifier Circuit ◽  
Folded Cascode ◽  
Noise Amplifier ◽  
5 Ghz

This paper is about Low noise amplifier topologies based on 0.18µm CMOS technology. A common source stage with inductive degeneration, cascode stage and folded cascode stage is designed, simulated and the performance has been analyzed. The LNA’s are designed in 5GHz. The LNA of cascode stage of noise figure (NF) 2.044dB and power gain 4.347 is achieved. The simulations are done in cadence virtuoso spectre RF.

scholarly journals A Low-Noise Amplifier Utilizing Current-Reuse Technique and Active Shunt Feedback for MedRadio Band Applications

2020 ◽  
pp. 306-316
Author(s):  
Mutanizam Abdul Mubin ◽  
◽  
Arjuna Marzuki
Keyword(s):  
Low Power ◽  
Return Loss ◽  
Noise Figure ◽  
High Gain ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Source ◽  
Cmos Process ◽  
Current Reuse ◽  
Noise Amplifier

In this work, a low-power 0.18-μm CMOS low-noise amplifier (LNA) for MedRadio applications has been designed and verified. Cadence IC5 software with Silterra’s C18G CMOS Process Design Kit were used for all design and simulation work. This LNA utilizes complementary common-source current-reuse topology and subthreshold biasing to achieve low-power operation with simultaneous high gain and low noise figure. An active shunt feedback circuit is used as input matching network to provide a suitable input return loss. For test and measurement purpose, an output buffer was designed and integrated with this LNA. Inductorless design approach of this LNA, together with the use of MOSCAPs as capacitors, help to minimize the die size. On post-layout simulations with LNA die area of 0.06 mm2 and simulated total DC power consumption of 0.5 mW, all targeted specifications are met. The simulated gain, input return loss and noise figure of this LNA are 16.3 dB, 10.1 dB and 4.9 dB respectively throughout the MedRadio frequency range. For linearity, the simulated input-referred P1dB of this LNA is -26.7 dBm while its simulated IIP3 is -18.6 dBm. Overall, the post-layout simulated performance of this proposed LNA is fairly comparable to some current state-of-the-art LNAs for MedRadio applications. The small die area of this proposed LNA is a significant improvement in comparison to those of the previously reported MedRadio LNAs.

scholarly journals Design and implementation of a broad-band high gain low noise amplifier for 3G/4G applications

2021 ◽  
Vol 23 (2) ◽  
pp. 725
Author(s):  
Ahmed M. Abdelmonem ◽  
Ahmed S. I. Amar ◽  
Amir Almslmany ◽  
Ibrahim L. Abdalla ◽  
Fathi A. Farag
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Low Cost ◽  
Broad Band ◽  
High Gain ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Design System ◽  
Matching Network ◽  
Noise Amplifier

The main aim of the paper is designing and implementing a broadband low-noise-amplifier (LNA) based on compensated matching network techniquein order to get high stable gain, low noise figure, low cost and smaller sizefor 3G/4G communication system applications at 2 GHz with bandwidth 600MHz. The Advanced Design System simulates the proposed circuit (ADS).The implementation was done with a class A bias circuit and a low noise transistor BFU 730F with a lower Noise Figure (NFmin) 0.62 dB. Collectorcurrent is measured to be 5.8mA and base current is 19.1μA with a supply voltage of 2.25V. The new design proposed a (NFmin) of 0.62 dB with a 17.8dB high stable amplifier gain. The microstrip lines (MSL) and compensated matching network techniques were used to improve the LNA’s stability and achieve a good result. The LNA board is implemented and assembled on the FR4 botton layer material. The results are virtually non existence equivalent between the simulated and the measured results.

scholarly journals Design of a LNA in the frequency band 1.8-2.2GHz in 0.13μm CMOS Technology

2005 ◽  
Vol 3 ◽  
pp. 299-303
Author(s):  
E. Di Gioia ◽  
C. Hermann ◽  
H. Klar
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Low Cost ◽  
Operating Mode ◽  
Cmos Technology ◽  
Digital Circuit ◽  
High Gain ◽  
Low Noise ◽  
Noise Amplifier ◽  
Low Supply Voltage

Abstract. The subject of this work is a low noise amplifier (LNA), operating in the frequency range 1.8-2.1GHz. The CMOS 0.13μm technology is used in respect to the low cost of the final device. Among the specifications, a variable gain and an adjustable working frequency are required. In particular, four different working modes are provided: 1.8, 1.9 and 2.1GHz high gain and 2.1GHz low gain. The amplifier is designed to be used as first stage of a receiver for mobile telephony. For this reason low power consumption is taken into consideration (low supply voltage and low drain currents). A simple digital circuit, integrated on-chip, is used to select the operating mode of the LNA by means of two input pins. A Noise figure of 1dB is obtained with a supply voltage of 0.8V.

scholarly journals Low Noise Amplifier with Improved Gain and Reduced Noise-Figure in 90nm CMOS Technology

2021 ◽  
pp. 85-94
Author(s):  
Dr. Rashmi S B ◽  
Mr. Raghavendra B ◽  
Mr. Sanketh V
Keyword(s):  
Reflection Coefficient ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Common Source ◽  
Frequency Range ◽  
Common Gate ◽  
Noise Amplifier

A CMOS low noise amplifier (LNA) for ultra-wideband (UWB) wireless applications is presented in this paper. The proposed CMOS low noise amplifier (LNA) is designed using common-gate (CG) topology as the first stage to achieve ultra-wideband input matching. The common-gate (CG) is cascaded with common- source (CS) topology with current-reused configuration to enhance the gain and noise figure (NF) performance of the LNA with low power. The Buffer stage is used as output matching network to improve the reflection coefficient. The proposed low noise amplifier (LNA) is implemented using CADENCE Virtuoso Analog and Digital Design Environment tool in 90nm CMOS technology. The LNA provides a forward voltage gain or power gain (S21) of 32.34dB , a minimum noise figure of 2dB, a reverse-isolation (S12) of less than - 38.74dB and an output reflection coefficient (S22) of less than -7.4dB for the entire ultra-wideband frequency range. The proposed LNA has an input reflection coefficient (S11) of less than -10dB for the ultra-wideband frequency range. It achieves input referred 1-dB compression point of 78.53dBm and input referred 3-dB compression point of 13dBm. It consumes only 24.226mW of power from a Vdd supply of 0.7V.

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