Improving Energy-Efficiency of Computational Grids via Scheduling

2010 ◽  
pp. 519-542 ◽  
Author(s):  
Ziliang Zong ◽  
Xiaojun Ruan ◽  
Adam Manzanares ◽  
Kiranmai Bellam ◽  
Xiao Qin
Keyword(s):  
Energy Efficiency ◽  
Energy Conservation ◽  
Grid Computing ◽  
Energy Efficient ◽  
High Speed ◽  
High Performance ◽  
Large Scale ◽  
Rapid Development ◽  
Computational Grids ◽  
Grid Architecture

High performance Grid platforms and parallel computing technologies are experiencing their golden age because of the convergence of four critical momentums: high performance microprocessors, high-speed networks, free middleware tools, and highly increased needs of computing capability. We are witnessing the rapid development of computational Grid technologies. Dozens of exciting Grid infrastructures and projects like Grid-tech, Grid Portals, Grid Fora, and Commercial Grid Initiatives are being built all over the world. However, the fast growing power consumption of data centers has caused serious concerns for building more large-scale supercomputers, clusters, and Grids. Therefore, designing energy-efficient computational Grids to make them economically attractive and environmentally friendly for parallel applications becomes highly desirable. Unfortunately, most previous studies in Grid computing primarily focus on the improvement of performance, security, and reliability, while completely ignoring the energy conservation issue. To address this problem, we propose a general architecture for building energy-efficient computational Grids and discuss the potential possibilities for incorporating power-aware techniques to different layers of the proposed Grid architecture. In this chapter, we first provide necessary background on computational Grids, Grid computing, and parallel scheduling. Next, we illustrate the general Grid architecture and explain the functionality of different layers. Followed by that, we discuss the design and implementation details of applying the energy-efficient job-scheduling technique, which is called Communication Energy Conservation Scheduling (or CECS for short), to computational Grids. Finally, we present extensive simulation results to prove the improvement of energy-efficiency of computational Grids.

Improving Energy-Efficiency of Computational Grids via Scheduling

2011 ◽  
pp. 1836-1857
Author(s):  
Ziliang Zong ◽  
Xiaojun Ruan ◽  
Adam Manzanares ◽  
Kiranmai Bellam ◽  
Xiao Qin
Keyword(s):  
Energy Efficiency ◽  
Energy Conservation ◽  
Grid Computing ◽  
Energy Efficient ◽  
High Speed ◽  
High Performance ◽  
Large Scale ◽  
Rapid Development ◽  
Computational Grids ◽  
Grid Architecture

High performance Grid platforms and parallel computing technologies are experiencing their golden age because of the convergence of four critical momentums: high performance microprocessors, high-speed networks, free middleware tools, and highly increased needs of computing capability. We are witnessing the rapid development of computational Grid technologies. Dozens of exciting Grid infrastructures and projects like Grid-tech, Grid Portals, Grid Fora, and Commercial Grid Initiatives are being built all over the world. However, the fast growing power consumption of data centers has caused serious concerns for building more large-scale supercomputers, clusters, and Grids. Therefore, designing energy-efficient computational Grids to make them economically attractive and environmentally friendly for parallel applications becomes highly desirable. Unfortunately, most previous studies in Grid computing primarily focus on the improvement of performance, security, and reliability, while completely ignoring the energy conservation issue. To address this problem, we propose a general architecture for building energy-efficient computational Grids and discuss the potential possibilities for incorporating power-aware techniques to different layers of the proposed Grid architecture. In this chapter, we first provide necessary background on computational Grids, Grid computing, and parallel scheduling. Next, we illustrate the general Grid architecture and explain the functionality of different layers. Followed by that, we discuss the design and implementation details of applying the energy-efficient job-scheduling technique, which is called Communication Energy Conservation Scheduling (or CECS for short), to computational Grids. Finally, we present extensive simulation results to prove the improvement of energy-efficiency of computational Grids.

scholarly journals Development of an Energy Efficient Stern Flap for Improved EEDI of a Typical High speed Displacement Vessel

2020 ◽  
Vol 70 (1) ◽  
pp. 95-102 ◽  
Author(s):  
Y. Hemanth Kumar ◽  
R. Vijaya Kumar
Keyword(s):  
Energy Efficiency ◽  
Fuel Consumption ◽  
Energy Efficient ◽  
High Speed ◽  
Large Scale ◽  
Operating Life ◽  
Cfd Simulations ◽  
Flap Design ◽  
Energy Efficiency Design Index ◽  
Fuel Consumption And Emissions

The surge in maritime trade is leading to large scale deployment of high-speed displacement ships by all nations. Cargo vessels are designed for a voyage in pre-determined routes at consistent speeds. On the other hand, high-speed displacement vessel engines designed with a capability to cater for top speeds are under-utilised during their normal course of operation. This sub-optimal utilisation impacts efficiency and increases emissions. In this study, a most favourable stern flap is designed for reducing the energy efficiency design index of a typical high-speed displacement vessel with a slender hull. CFD simulations and experimental model testing were conducted for 12 different stern flap configurations for determining most favourable flap design in the Froude no of 0.17-0.48. Performance of the most favourable stern flap was established by calculating, energy efficiency design index (EEDI) and fuel consumption based on typical operating profile. NOx, VOC and PM emissions were estimated in with and without flap condition. Studies demonstrated that the stern flap reduced effective power demand, average fuel consumption and emissions by about 8 per cent, which when considered for the ship’s operating life cycle, are significant. The most favourable stern flap reduced EEDI by 3.74 units and 1.98 units as compared to the bare hull condition and the required EEDI respectively, thereby demonstrating that EEDI could be used as an index to indicate stern flap efficiency.

scholarly journals Statistical and machine learning models for optimizing energy in parallel applications

2019 ◽  
Vol 33 (6) ◽  
pp. 1079-1097 ◽  
Author(s):  
Mark Endrei ◽  
Chao Jin ◽  
Minh Ngoc Dinh ◽  
David Abramson ◽  
Heidi Poxon ◽  
...  
Keyword(s):  
Machine Learning ◽  
Energy Efficiency ◽  
High Performance ◽  
Large Scale ◽  
Energy Use ◽  
Parallel Applications ◽  
Learning Models ◽  
Trade Off ◽  
Time Required ◽  
Machine Learning Models

Rising power costs and constraints are driving a growing focus on the energy efficiency of high performance computing systems. The unique characteristics of a particular system and workload and their effect on performance and energy efficiency are typically difficult for application users to assess and to control. Settings for optimum performance and energy efficiency can also diverge, so we need to identify trade-off options that guide a suitable balance between energy use and performance. We present statistical and machine learning models that only require a small number of runs to make accurate Pareto-optimal trade-off predictions using parameters that users can control. We study model training and validation using several parallel kernels and more complex workloads, including Algebraic Multigrid (AMG), Large-scale Atomic Molecular Massively Parallel Simulator, and Livermore Unstructured Lagrangian Explicit Shock Hydrodynamics. We demonstrate that we can train the models using as few as 12 runs, with prediction error of less than 10%. Our AMG results identify trade-off options that provide up to 45% improvement in energy efficiency for around 10% performance loss. We reduce the sample measurement time required for AMG by 90%, from 13 h to 74 min.

scholarly journals Catalytic production of impurity-free V3.5+ electrolyte for vanadium redox flow batteries

2019 ◽  
Vol 10 (1) ◽  
Author(s):  
Jiyun Heo ◽  
Jae-Yun Han ◽  
Soohyun Kim ◽  
Seongmin Yuk ◽  
Chanyong Choi ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Large Scale ◽  
Catalytic Reduction ◽  
Continuous Production ◽  
Vanadium Redox Flow Battery ◽  
Manufacturing Cost ◽  
Chemical Production ◽  
High Manufacturing Cost ◽  
Vanadium Redox

Abstract The vanadium redox flow battery is considered one of the most promising candidates for use in large-scale energy storage systems. However, its commercialization has been hindered due to the high manufacturing cost of the vanadium electrolyte, which is currently prepared using a costly electrolysis method with limited productivity. In this work, we present a simpler method for chemical production of impurity-free V3.5+ electrolyte by utilizing formic acid as a reducing agent and Pt/C as a catalyst. With the catalytic reduction of V4+ electrolyte, a high quality V3.5+ electrolyte was successfully produced and excellent cell performance was achieved. Based on the result, a prototype catalytic reactor employing Pt/C-decorated carbon felt was designed, and high-speed, continuous production of V3.5+ electrolyte in this manner was demonstrated with the reactor. This invention offers a simple but practical strategy to reduce the production cost of V3.5+ electrolyte while retaining quality that is adequate for high-performance operations.

FPGA-Based Intelligent Software Hardening Chip for Computer Numerical Control System

2011 ◽  
Vol 105-107 ◽  
pp. 2217-2220
Author(s):  
Mu Lan Wang ◽  
Jian Min Zuo ◽  
Kun Liu ◽  
Xing Hua Zhu
Keyword(s):  
High Speed ◽  
High Performance ◽  
Large Scale ◽  
Position Control ◽  
Computer Numerical Control ◽  
Numerical Control ◽  
Cnc Machine Tools ◽  
Cnc Machine ◽  
Cnc System ◽  
Intelligent Software

In order to meet the development demands for high-speed and high-precision of Computer Numerical Control (CNC) machine tools, the equipped CNC systems begin to employ the technical route of software hardening. Making full use of the advanced performance of Large Scale Integrated Circuits (LSIC), this paper puts forward using Field Programmable Gates Array (FPGA) for the functional modules of CNC system, which is called Intelligent Software Hardening Chip (ISHC). The CNC system architecture with high performance is constructed based on the open system thought and ISHCs. The corresponding programs can be designed with Very high speed integrate circuit Hardware Description Language (VHDL) and downloaded into the FPGA. These hardening modules, including the arithmetic module, contour interpolation module, position control module and so on, demonstrate that the proposed schemes are reasonable and feasibility.

Towards A Multi-FPGA Infrared Simulator

2007 ◽  
Vol 4 (4) ◽  
pp. 343-355 ◽  
Author(s):  
Vinay Sriram ◽  
David Kearney
Keyword(s):  
Homeland Security ◽  
Reconfigurable Computing ◽  
High Speed ◽  
High Performance ◽  
Large Scale ◽  
Computation Time ◽  
Ccd Camera ◽  
Hardware Acceleration ◽  
Limiting Factor ◽  
Scene Simulation

High speed infrared (IR) scene simulation is used extensively in defense and homeland security to test sensitivity of IR cameras and accuracy of IR threat detection and tracking algorithms used commonly in IR missile approach warning systems (MAWS). A typical MAWS requires an input scene rate of over 100 scenes/second. Infrared scene simulations typically take 32 minutes to simulate a single IR scene that accounts for effects of atmospheric turbulence, refraction, optical blurring and charge-coupled device (CCD) camera electronic noise on a Pentium 4 (2.8GHz) dual core processor [7]. Thus, in IR scene simulation, the processing power of modern computers is a limiting factor. In this paper we report our research to accelerate IR scene simulation using high performance reconfigurable computing. We constructed a multi Field Programmable Gate Array (FPGA) hardware acceleration platform and accelerated a key computationally intensive IR algorithm over the hardware acceleration platform. We were successful in reducing the computation time of IR scene simulation by over 36%. This research acts as a unique case study for accelerating large scale defense simulations using a high performance multi-FPGA reconfigurable computer.

scholarly journals BUILDING ENERGY AND ARCHITECTURAL FORM RELATIONSHIPS / PASTATO ENERGIJOS IR ARCHITEKTŪRINĖS FORMOS RYŠIAI

2011 ◽  
Vol 3 (3) ◽  
pp. 67-71 ◽  
Author(s):  
Roberts Riekstiņš
Keyword(s):  
Energy Efficiency ◽  
Environmental Sustainability ◽  
Energy Efficient ◽  
Large Scale ◽  
Building Energy ◽  
Substantial Part ◽  
Building Energy Efficiency ◽  
Total Energy Consumption ◽  
Architectural Form ◽  
Energy Efficient Building

Energy efficiency of buildings, of course, is now a major issue in the construction industry. It is being widely examined both among construction professionals and amateurs. There is no doubt that energy efficiency as a key factor in ensuring environmental sustainability will become the main driving force of the construction in the future. Buildings have to become more energy-efficient. This opinion is supported by the existing energy-use balance in Europe, indicating that the housing sector spends almost half of total energy consumption and building sector forms more than a third of total CO2 emissions (Bradley 2010). While discussing the subject of building energy efficiency, mostly different technical characteristics of buildings and engineering solutions are talked over. However, it has been relatively little examined how energy-efficient design affects the building’s architecturally-aesthetic side, styles of expression and trends in the architect’s profession. We learn that the essence for an energy-efficient building lies in smart modesty (Bokalders, Block 2010) and the rational utilization of materials (aim high – go low). And still – can energy efficient building be expressive, extravagant, and perhaps – even ambitious? There are many ideas implemented in projects which show that energy efficiency is not an obstacle to large scale architectural ideas. However, in order to combine architectural and artistic ambitions with the principles of sustainability, architects should search for an entirely new approach to architectural expression based on a detailed assessment of solutions applied from environmental point of view. It requires a complex understanding of building shape, applied technologies, energetic benefits and cost parameters. This article identifies the realised and experimental projects of the world and presents an analysis of classification of buildings according to typology. This publication gives general impression of the amplitude and topicality of the study issue, as well as the diversity applied to the architectural techniques. The article concludes that even creating a building’s shape in a smart way makes it possible to use substantial part of the renewable energy offered by nature.

Design of a Digital Audio Player Based on μc/Os and μc/GUI

2013 ◽  
Vol 462-463 ◽  
pp. 650-653
Author(s):  
Shao Yuan Li
Keyword(s):  
High Speed ◽  
High Performance ◽  
Rapid Development ◽  
Digital Audio ◽  
Embedded Operating System ◽  
Audio Processing ◽  
Audio Technology ◽  
Machine Interface ◽  
Audio Decoder ◽  
Sd Card

At present, with the rapid development of digital audio technology, high speed and high performance digital audio processing technology faces an important issue. This paper proposes and designs a digital audio player combined with digital audio and embedded systems two cutting-edge technology. Hardware circuitry takes STM32F103VE as the main controller, configurated with VS1003 audio decoder chip and the corresponding SD card storage module, LCD module, power supply module and so on; software design transplants embedded operating system μC / OS. This paper takes advantage of μC/GUI to design audio player graphical user interface, improves the human-machine interface friendliness and aesthetics greatly.

scholarly journals A parallel computational framework for ultra-large-scale sequence clustering analysis

2018 ◽  
Vol 35 (3) ◽  
pp. 380-388 ◽  
Author(s):  
Wei Zheng ◽  
Qi Mao ◽  
Robert J Genco ◽  
Jean Wactawski-Wende ◽  
Michael Buck ◽  
...  
Keyword(s):  
Parallel Computing ◽  
High Performance ◽  
Large Scale ◽  
De Novo ◽  
Rapid Development ◽  
Operational Taxonomic Unit ◽  
Supplementary Information ◽  
Computational Framework ◽  
Speed Up ◽  
Scale Sequence

Abstract Motivation The rapid development of sequencing technology has led to an explosive accumulation of genomic data. Clustering is often the first step to be performed in sequence analysis. However, existing methods scale poorly with respect to the unprecedented growth of input data size. As high-performance computing systems are becoming widely accessible, it is highly desired that a clustering method can easily scale to handle large-scale sequence datasets by leveraging the power of parallel computing. Results In this paper, we introduce SLAD (Separation via Landmark-based Active Divisive clustering), a generic computational framework that can be used to parallelize various de novo operational taxonomic unit (OTU) picking methods and comes with theoretical guarantees on both accuracy and efficiency. The proposed framework was implemented on Apache Spark, which allows for easy and efficient utilization of parallel computing resources. Experiments performed on various datasets demonstrated that SLAD can significantly speed up a number of popular de novo OTU picking methods and meanwhile maintains the same level of accuracy. In particular, the experiment on the Earth Microbiome Project dataset (∼2.2B reads, 437 GB) demonstrated the excellent scalability of the proposed method. Availability and implementation Open-source software for the proposed method is freely available at https://www.acsu.buffalo.edu/~yijunsun/lab/SLAD.html. Supplementary information Supplementary data are available at Bioinformatics online.

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