scholarly journals Design of a low-power flash analog-to-digital converter chip for temperature sensors in 0.18 µm CMOS process

2015 ◽  
Vol 37 (1) ◽  
pp. 33 ◽  
Author(s):  
Al Al ◽  
Mamun Bin Ibne Reaz ◽  
Jubayer Jalil ◽  
Mohd. Alauddin Mohd. Ali
Keyword(s):  
Low Power ◽  
Temperature Sensors ◽  
Cmos Process ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital

AN OPTIMIZED LOW POWER PIPELINE ANALOG-TO-DIGITAL CONVERTER FOR HIGH-SPEED WLAN APPLICATION

2014 ◽  
Vol 23 (05) ◽  
pp. 1450059 ◽  
Author(s):  
MAO YE ◽  
BIN WU ◽  
YONGXU ZHU ◽  
YUMEI ZHOU
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Dynamic Range ◽  
Cmos Process ◽  
Area Network ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Silicon Area ◽  
Analog To Digital

This paper presents the design and implementation of a 11-bit 160 MSPS analog-to-digital converter (ADC) for next generation super high-speed wireless local area network (WLAN) application. The ADC core consists of one front sample and hold stage and four cascades of 2.5 bit pipeline stages with opamp sharing between successive stages. To achieve low power dissipation at 1.2 V supply, a single stage symmetrical amplifier with double transimpedance gain-boosting amplifier is proposed. High speed on-chip reference buffer with replica source follower is also included for linearity performance. The ADC was fabricated in a standard 130-nm CMOS process and an occupied silicon area of 0.95 mm × 1.15 mm. Performance of 73 dB spurious-free-dynamic-range is measured at 160 MS/s with 1 Vpp input signal. The power dissipation of the analog core chip is only 50 mW from a 1.2 V supply.

scholarly journals Ein 10 bit 10MS/s Low-Power AD-Converter in 0.11mm2

2005 ◽  
Vol 2 ◽  
pp. 205-209
Author(s):  
D. Muthers ◽  
R. Tielert
Keyword(s):  
Low Power ◽  
Small Area ◽  
Digital Filters ◽  
Cmos Process ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Mixed Signal ◽  
Analog To Digital ◽  
Ad Converter ◽  
Mim Capacitors

Abstract. Ein 10 bit 10MS/s Analog-Digital- Wandler mit niedriger Leistungaufnahme von 8,4mW wurde implementiert. Der geringe Flächenbedarf von 0,11mm2 macht diesen Wandler besonders geeignet f¨ur Multikanalanwendungen. Um die Anforderungen von 10 bit, 10 MS/s möglichst effizient zu erfüllen wurde eine zyklische Wandlerarchitektur gewählt, die in einem 0,18μm-CMOSProzess mit MIM-Kondensatoren implementiert wurde. Der entworfene ADC wurde in 21 parallelen Kanälen auf einem mixed-signal-Chip zusammen mit digitalen Filtern, vier RISC-CPUs und I/O-Schaltungen implementiert. A 10 bit 10MS/s Analog to Digital Converter, consuming a power of 8,4mW, has been implemented. Due to the small area of 0,11mm2 this ADC is highly suited for multichannel implementations. A cyclic converter architecture is best suited for this application, being implemented in a 0,18μm CMOS process with MIM-capacitors. The designed ADC was implemented in an array of 21 channels on a mixed signal chip together with digital filters, four RISC-CPUs and I/O circuitry.

A novel time-based low-power pipeline analog to digital converter

2009 ◽  
Vol 62 (3) ◽  
pp. 281-289 ◽  
Author(s):  
Mohammad Hossein Zarifi ◽  
Javad Frounchi ◽  
Shahin Farshchi ◽  
Jack W. Judy
Keyword(s):  
Low Power ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital
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