Detector on Dam’s Piezometric Tube Level

2012 ◽  
Vol 214 ◽  
pp. 730-734
Author(s):  
Lin Sheng Wang ◽  
Dong He Xi ◽  
Lin Jing Wang
Keyword(s):  
Computer Technology ◽  
High Speed ◽  
Digital Signal ◽  
Single Pulse ◽  
Digital Measuring ◽  
Single Chip ◽  
Piezometric Level ◽  
Detection Technology ◽  
Single Chip Computer ◽  
High Degree

The change of reservoir dam’s piezometric level can reflect the dam’s internal structure, piezometric level number obtained by using detection technology can directly judge the interior defect, therefore, whether piezometric level detection is accurate or not is related to dam’s safety. After years’ research, the design scheme of integrating mechanics and electrics is put forward by combining with today’s popular single chip computer technology and digital measuring technology, which is the scheme that we adopt the digital detection technology to convert the water level into pulse digital signal directly and calculate the piezometric level according to the number of single pulse. It is necessary to develop a Piezometric Tube detector with teatures of high precision, high degree of automation and high speed of processing and acquisiting data and put it into use.

The Application of FPGA and DSP Techniques in Intelligent Wattmeter

2011 ◽  
Vol 201-203 ◽  
pp. 2096-2100 ◽  
Author(s):  
Hui Rong Li ◽  
Li Juan Pang ◽  
Xue Feng Zhang ◽  
Gang Deng ◽  
Yan Wei Tong
Keyword(s):  
Power System ◽  
Data Acquisition ◽  
High Speed ◽  
Processing System ◽  
Single Chip ◽  
Measuring Accuracy ◽  
Single Chip Computer ◽  
Time Calculation ◽  
Higher Harmonic ◽  
Data Acquisition And Processing

According to the demand of data acquisition in power system, the intelligent wattmeter is constructed, which is based on DSP and FPGA as the data acquisition and processing system, meanwhile, the administration center of the intelligent wattmeter is based on single-chip computer 8051. With these, high speed, multi-point sampling, a large quantity accumulation and real-time calculation are realized. At the same time it reduces the effect of the measuring accuracy upon higher harmonic and the measuring accuracy could reach to 0.02 grade.

scholarly journals Area Efficient High Speed Vedic Multiplier

2019 ◽  
Vol 8 (9S) ◽  
pp. 302-306
Keyword(s):  
High Speed ◽  
Large Scale ◽  
Arithmetic Operation ◽  
Vlsi Design ◽  
Digital Signal ◽  
Digital Circuit ◽  
Single Chip ◽  
Digital Vlsi ◽  
Large Scale Integration ◽  
Scale Integration

Very large scale integration is a process of integrating hundreds of thousands of transistors or devices into a single chip. VLSI can be categorized into two fields Frontend and Backend. Digital VLSI design falls under the Frontend design. Multiplication is an arithmetic operation important for the Digital Signal Processing (DSP) and for processors. Multiplier is the main hardware block for the digital circuit. More than 70% of the applications in a digital circuit are either addition or multiplication. As these operations dominates most of the execution time so we need fast multipliers. The overall objective of a good multiplier is to have high speed, low power consumption unit, less area. Vedic multipliers are the fast multipliers and occupy less area. They are based on the Vedic mathematics sutra "Urdhava-Triyakbhyam" . The paper contain a high speed multipliers and use of different adder structures.

scholarly journals The Development of a High Performance Digital RF Transmitter for NMR

2021 ◽  
Author(s):  
◽  
Shaw Wei Cheoo
Keyword(s):  
High Speed ◽  
High Performance ◽  
Research Work ◽  
Digital Signal ◽  
Electronic Subsystem ◽  
Single Chip ◽  
Direct Digital Synthesis ◽  
Rf Transmitter ◽  
Master's Thesis ◽  
Field Programmable

<p>This Master’s thesis consists of the development of a Nuclear Magnetic Resonance (NMR) Radio Frequency (RF) transmitter, which is a core electronic subsystem of an NMR system. The main purpose of this research is to contribute to the application of NMR, which is a new sensing technology that has yet to be fully implemented into the everyday world. One of the barriers to adopting this technology is its complexity. However, the invention of high speed digital FPGAs (Field Programmable Gate Array) such as the Spartan series has made it easier to develop high performance NMR systems over recent years. The major contribution to this research is the development of faster digital signal processing hardware, and methodologies that have been implemented on a single chip. This has reduced the size and the cost of the electronic subsystem and contributed towards the evolution of NMR as a general tool. This thesis introduces the concept of implementing a high-speed NMR RF multi-frequency transmitter by using multiple Direct Digital Synthesis (DDS) cores to generate sine-waves, which range from 100 kHz to 750 MHz. The research required three stages to be achieved, beginning with conceptual design of a high-speed transmitter using MATLAB-Simulink, RTL-level (Register-Transfer Level) simulation and hardware implementation, which included hardware testing on a prototype board. This Master’s research is to seek a solution to building a multi-core DDS module in an FPGA device. In other words, the research work focuses on finding an alternative solution to constructing a DDS system. The project involves building up the VHSIC Hardware Description Language (VHDL) program to work beyond the hardware limitation of an FPGA device. Hence, the final solution does not consider any noise impact due to the structure of the developed system.</p>

scholarly journals The Development of a High Performance Digital RF Transmitter for NMR

2021 ◽  
Author(s):  
◽  
Shaw Wei Cheoo
Keyword(s):  
High Speed ◽  
High Performance ◽  
Research Work ◽  
Digital Signal ◽  
Electronic Subsystem ◽  
Single Chip ◽  
Direct Digital Synthesis ◽  
Rf Transmitter ◽  
Master's Thesis ◽  
Field Programmable

<p>This Master’s thesis consists of the development of a Nuclear Magnetic Resonance (NMR) Radio Frequency (RF) transmitter, which is a core electronic subsystem of an NMR system. The main purpose of this research is to contribute to the application of NMR, which is a new sensing technology that has yet to be fully implemented into the everyday world. One of the barriers to adopting this technology is its complexity. However, the invention of high speed digital FPGAs (Field Programmable Gate Array) such as the Spartan series has made it easier to develop high performance NMR systems over recent years. The major contribution to this research is the development of faster digital signal processing hardware, and methodologies that have been implemented on a single chip. This has reduced the size and the cost of the electronic subsystem and contributed towards the evolution of NMR as a general tool. This thesis introduces the concept of implementing a high-speed NMR RF multi-frequency transmitter by using multiple Direct Digital Synthesis (DDS) cores to generate sine-waves, which range from 100 kHz to 750 MHz. The research required three stages to be achieved, beginning with conceptual design of a high-speed transmitter using MATLAB-Simulink, RTL-level (Register-Transfer Level) simulation and hardware implementation, which included hardware testing on a prototype board. This Master’s research is to seek a solution to building a multi-core DDS module in an FPGA device. In other words, the research work focuses on finding an alternative solution to constructing a DDS system. The project involves building up the VHSIC Hardware Description Language (VHDL) program to work beyond the hardware limitation of an FPGA device. Hence, the final solution does not consider any noise impact due to the structure of the developed system.</p>

Efficient Computing in Image Processing and DSPs with ASIP Based Multiplier

2019 ◽  
Vol 13 (2) ◽  
pp. 174-180
Author(s):  
Poonam Sharma ◽  
Ashwani Kumar Dubey ◽  
Ayush Goyal
Keyword(s):  
Image Processing ◽  
High Speed ◽  
Computation Time ◽  
Digital Signal ◽  
Instruction Set ◽  
Computationally Efficient ◽  
Specific Instruction ◽  
Processor Core ◽  
Speed Performance ◽  
Application Specific

Background: With the growing demand of image processing and the use of Digital Signal Processors (DSP), the efficiency of the Multipliers and Accumulators has become a bottleneck to get through. We revised a few patents on an Application Specific Instruction Set Processor (ASIP), where the design considerations are proposed for application-specific computing in an efficient way to enhance the throughput. Objective: The study aims to develop and analyze a computationally efficient method to optimize the speed performance of MAC. Methods: The work presented here proposes the design of an Application Specific Instruction Set Processor, exploiting a Multiplier Accumulator integrated as the dedicated hardware. This MAC is optimized for high-speed performance and is the application-specific part of the processor; here it can be the DSP block of an image processor while a 16-bit Reduced Instruction Set Computer (RISC) processor core gives the flexibility to the design for any computing. The design was emulated on a Xilinx Field Programmable Gate Array (FPGA) and tested for various real-time computing. Results: The synthesis of the hardware logic on FPGA tools gave the operating frequencies of the legacy methods and the proposed method, the simulation of the logic verified the functionality. Conclusion: With the proposed method, a significant improvement of 16% increase in throughput has been observed for 256 steps iterations of multiplier and accumulators on an 8-bit sample data. Such an improvement can help in reducing the computation time in many digital signal processing applications where multiplication and addition are done iteratively.

scholarly journals Three-Axis Inductive Displacement Sensor Using Phase-Sensitive Digital Signal Processing for Industrial Magnetic Bearing Applications

Actuators ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 115
Author(s):  
Teemu Sillanpää ◽  
Alexander Smirnov ◽  
Pekko Jaatinen ◽  
Jouni Vuojolainen ◽  
Niko Nevaranta ◽  
...  
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Eddy Current ◽  
High Speed ◽  
Digital Signal ◽  
Magnetic Bearing ◽  
Air Gap ◽  
Sensor Design ◽  
Quadrature Demodulation ◽  
Displacement Sensors

Non-contact rotor position sensors are an essential part of control systems in magnetically suspended high-speed drives. In typical active magnetic bearing (AMB) levitated high-speed machine applications, the displacement of the rotor in the mechanical air gap is measured with commercially available eddy current-based displacement sensors. The aim of this paper is to propose a robust and compact three-dimensional position sensor that can measure the rotor displacement of an AMB system in both the radial and axial directions. The paper presents a sensor design utilizing only a single unified sensor stator and a single shared rotor mounted target piece surface to achieve the measurement of all three measurement axes. The sensor uses an inductive measuring principle to sense the air gap between the sensor stator and rotor piece, which makes it robust to surface variations of the sensing target. Combined with the sensor design, a state of the art fully digital signal processing chain utilizing synchronous in-phase and quadrature demodulation is presented. The feasibility of the proposed sensor design is verified in a closed-loop control application utilizing a 350-kW, 15,000-r/min high-speed industrial induction machine with magnetic bearing suspension. The inductive sensor provides an alternative solution to commercial eddy current displacement sensors. It meets the application requirements and has a robust construction utilizing conventional electrical steel lamination stacks and copper winding.

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