scholarly journals The Development of a High Performance Digital RF Transmitter for NMR

2021 ◽  
Author(s):  
◽  
Shaw Wei Cheoo
Keyword(s):  
High Speed ◽  
High Performance ◽  
Research Work ◽  
Digital Signal ◽  
Electronic Subsystem ◽  
Single Chip ◽  
Direct Digital Synthesis ◽  
Rf Transmitter ◽  
Master's Thesis ◽  
Field Programmable

<p>This Master’s thesis consists of the development of a Nuclear Magnetic Resonance (NMR) Radio Frequency (RF) transmitter, which is a core electronic subsystem of an NMR system. The main purpose of this research is to contribute to the application of NMR, which is a new sensing technology that has yet to be fully implemented into the everyday world. One of the barriers to adopting this technology is its complexity. However, the invention of high speed digital FPGAs (Field Programmable Gate Array) such as the Spartan series has made it easier to develop high performance NMR systems over recent years. The major contribution to this research is the development of faster digital signal processing hardware, and methodologies that have been implemented on a single chip. This has reduced the size and the cost of the electronic subsystem and contributed towards the evolution of NMR as a general tool. This thesis introduces the concept of implementing a high-speed NMR RF multi-frequency transmitter by using multiple Direct Digital Synthesis (DDS) cores to generate sine-waves, which range from 100 kHz to 750 MHz. The research required three stages to be achieved, beginning with conceptual design of a high-speed transmitter using MATLAB-Simulink, RTL-level (Register-Transfer Level) simulation and hardware implementation, which included hardware testing on a prototype board. This Master’s research is to seek a solution to building a multi-core DDS module in an FPGA device. In other words, the research work focuses on finding an alternative solution to constructing a DDS system. The project involves building up the VHSIC Hardware Description Language (VHDL) program to work beyond the hardware limitation of an FPGA device. Hence, the final solution does not consider any noise impact due to the structure of the developed system.</p>

scholarly journals The Development of a High Performance Digital RF Transmitter for NMR

2021 ◽  
Author(s):  
◽  
Shaw Wei Cheoo
Keyword(s):  
High Speed ◽  
High Performance ◽  
Research Work ◽  
Digital Signal ◽  
Electronic Subsystem ◽  
Single Chip ◽  
Direct Digital Synthesis ◽  
Rf Transmitter ◽  
Master's Thesis ◽  
Field Programmable

<p>This Master’s thesis consists of the development of a Nuclear Magnetic Resonance (NMR) Radio Frequency (RF) transmitter, which is a core electronic subsystem of an NMR system. The main purpose of this research is to contribute to the application of NMR, which is a new sensing technology that has yet to be fully implemented into the everyday world. One of the barriers to adopting this technology is its complexity. However, the invention of high speed digital FPGAs (Field Programmable Gate Array) such as the Spartan series has made it easier to develop high performance NMR systems over recent years. The major contribution to this research is the development of faster digital signal processing hardware, and methodologies that have been implemented on a single chip. This has reduced the size and the cost of the electronic subsystem and contributed towards the evolution of NMR as a general tool. This thesis introduces the concept of implementing a high-speed NMR RF multi-frequency transmitter by using multiple Direct Digital Synthesis (DDS) cores to generate sine-waves, which range from 100 kHz to 750 MHz. The research required three stages to be achieved, beginning with conceptual design of a high-speed transmitter using MATLAB-Simulink, RTL-level (Register-Transfer Level) simulation and hardware implementation, which included hardware testing on a prototype board. This Master’s research is to seek a solution to building a multi-core DDS module in an FPGA device. In other words, the research work focuses on finding an alternative solution to constructing a DDS system. The project involves building up the VHSIC Hardware Description Language (VHDL) program to work beyond the hardware limitation of an FPGA device. Hence, the final solution does not consider any noise impact due to the structure of the developed system.</p>

scholarly journals DESIGN OF HIGH PERFORMANCE MULTIPLIERLESS LINEAR PHASE FINITE IMPULSE RESPONSE FILTERS

2017 ◽  
Vol 10 (13) ◽  
pp. 66
Author(s):  
A Aparna ◽  
T Vigneswaran
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
High Speed ◽  
High Performance ◽  
Finite Impulse Response ◽  
Research Work ◽  
Digital Signal ◽  
Fir Filter ◽  
Pass Filter ◽  
Finite Impulse Response Filters

This research work proposes the finite impulse response (FIR) filters design using distributed arithmetic architecture optimized for field programmable gate array. To implement computationally efficient, low power, high-speed FIR filter a two-dimensional fully pipelined structure is used. The FIR filter is dynamically reconfigured to realize low pass and high pass filter by changing the filter coefficients. The FIR filter is most fundamental components in digital signal processing for high-speed application. The aim of this research work is to design multiplier-less FIR filter for the requirements of low power and high speed various embedded applications. 

scholarly journals Embedded GPU Implementation for High-Performance Ultrasound Imaging

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 884
Author(s):  
Stefano Rossi ◽  
Enrico Boni
Keyword(s):  
High Performance ◽  
Graphics Processing Unit ◽  
Digital Signal ◽  
Processing Unit ◽  
Embedded Computing ◽  
Field Programmable ◽  
Peripheral Component Interconnect ◽  
Programmable Gate Arrays ◽  
Graphics Processing ◽  
Signal Processors

Methods of increasing complexity are currently being proposed for ultrasound (US) echographic signal processing. Graphics Processing Unit (GPU) resources allowing massive exploitation of parallel computing are ideal candidates for these tasks. Many high-performance US instruments, including open scanners like ULA-OP 256, have an architecture based only on Field-Programmable Gate Arrays (FPGAs) and/or Digital Signal Processors (DSPs). This paper proposes the implementation of the embedded NVIDIA Jetson Xavier AGX module on board ULA-OP 256. The system architecture was revised to allow the introduction of a new Peripheral Component Interconnect Express (PCIe) communication channel, while maintaining backward compatibility with all other embedded computing resources already on board. Moreover, the Input/Output (I/O) peripherals of the module make the ultrasound system independent, freeing the user from the need to use an external controlling PC.

scholarly journals A Review of Self-Coherent Optical Transceivers: Fundamental Issues, Recent Advances, and Research Directions

2021 ◽  
Vol 11 (16) ◽  
pp. 7554
Author(s):  
Isiaka Alimi ◽  
Romil Patel ◽  
Nuno Silva ◽  
Chuanbowen Sun ◽  
Honglin Ji ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Dynamic Environment ◽  
Digital Signal ◽  
Research Directions ◽  
Recent Advances ◽  
Heterogeneous Nature ◽  
Signal Processing Algorithms ◽  
Processing Algorithms

This paper reviews recent progress on different high-speed optical short- and medium-reach transmission systems. Furthermore, a comprehensive tutorial on high-performance, low-cost, and advanced optical transceiver (TRx) paradigms is presented. In this context, recent advances in high-performance digital signal processing algorithms and innovative optoelectronic components are extensively discussed. Moreover, based on the growing increase in the dynamic environment and the heterogeneous nature of different applications and services to be supported by the systems, we discuss the reconfigurable and sliceable TRxs that can be employed. The associated technical challenges of various system algorithms are reviewed, and we proffer viable solutions to address them.

scholarly journals Efficient Implementation of Multichannel FM and T-DMB Repeater in FPGA with Automatic Gain Controller

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 482
Author(s):  
Mangi Han ◽  
Youngmin Kim
Keyword(s):  
High Performance ◽  
Electronic Device ◽  
Finite Impulse Response ◽  
Parallel Implementation ◽  
Power Level ◽  
Digital Signal ◽  
Digital Circuit ◽  
Output Power Level ◽  
Verilog Hdl ◽  
Field Programmable

In this study, we implemented a high-performance multichannel repeater, both for FM and T-Digital Multimedia Broadcasting (DMB) signals using a Field Programmable Gate Array (FPGA). In a system for providing services using wireless communication, a radio-shaded area is inevitably generated due to various obstacles. Thus, an electronic device that receives weak or low-level signals and retransmits them at a higher level is crucial. In addition, parallel implementation of digital filters and gain controllers is necessary for a multichannel repeater. When power level is too low or too high, the repeater is required to compensate the power level and ensure a stable signal. However, analog- and software-based repeaters are expensive and they are difficult to install. They also cannot effectively process multichannel in parallel. The proposed system exploits various digital signal-processing algorithms, which include modulation, demodulation, Cascaded Integrator Comb (CIC) filters, Finite Impulse Response (FIR) filters, Interpolated Second Ordered Polynomials (ISOP) filters, and Automatic Gain Controllers (AGCs). The newly proposed AGC is more efficient than others in terms of computation amount and throughput. The designed digital circuit was implemented by using Verilog HDL, and tested using a Xilinx Kintex 7 device. As a result, the proposed repeater can simultaneously handle 40 FM channels and 6 DMB channels in parallel. Output power level is also always maintained by the AGC.

Detector on Dam’s Piezometric Tube Level

2012 ◽  
Vol 214 ◽  
pp. 730-734
Author(s):  
Lin Sheng Wang ◽  
Dong He Xi ◽  
Lin Jing Wang
Keyword(s):  
Computer Technology ◽  
High Speed ◽  
Digital Signal ◽  
Single Pulse ◽  
Digital Measuring ◽  
Single Chip ◽  
Piezometric Level ◽  
Detection Technology ◽  
Single Chip Computer ◽  
High Degree

The change of reservoir dam’s piezometric level can reflect the dam’s internal structure, piezometric level number obtained by using detection technology can directly judge the interior defect, therefore, whether piezometric level detection is accurate or not is related to dam’s safety. After years’ research, the design scheme of integrating mechanics and electrics is put forward by combining with today’s popular single chip computer technology and digital measuring technology, which is the scheme that we adopt the digital detection technology to convert the water level into pulse digital signal directly and calculate the piezometric level according to the number of single pulse. It is necessary to develop a Piezometric Tube detector with teatures of high precision, high degree of automation and high speed of processing and acquisiting data and put it into use.

Implementation of Embedded Floating Point Arithmetic Units on FPGA

2014 ◽  
Vol 550 ◽  
pp. 126-136
Author(s):  
N. Ramya Rani
Keyword(s):  
High Speed ◽  
High Performance ◽  
Floating Point ◽  
Double Precision ◽  
Embedded Computing ◽  
Floating Point Arithmetic ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Arithmetic Units ◽  
Point Arithmetic

:Floating point arithmetic plays a major role in scientific and embedded computing applications. But the performance of field programmable gate arrays (FPGAs) used for floating point applications is poor due to the complexity of floating point arithmetic. The implementation of floating point units on FPGAs consumes a large amount of resources and that leads to the development of embedded floating point units in FPGAs. Embedded applications like multimedia, communication and DSP algorithms use floating point arithmetic in processing graphics, Fourier transformation, coding, etc. In this paper, methodologies are presented for the implementation of embedded floating point units on FPGA. The work is focused with the aim of achieving high speed of computations and to reduce the power for evaluating expressions. An application that demands high performance floating point computation can achieve better speed and density by incorporating embedded floating point units. Additionally this paper describes a comparative study of the design of single precision and double precision pipelined floating point arithmetic units for evaluating expressions. The modules are designed using VHDL simulation in Xilinx software and implemented on VIRTEX and SPARTAN FPGAs.

scholarly journals Review on the Effect of the Phenomenon of Cavitation in Combustion Efficiency and the Role of Biofuels as a Solution against Cavitation

Energies ◽  
2021 ◽  
Vol 14 (21) ◽  
pp. 7265
Author(s):  
Ludovic Lamoot ◽  
Brady Manescau ◽  
Khaled Chetehouna ◽  
Nicolas Gascoin
Keyword(s):  
High Speed ◽  
High Performance ◽  
Research Work ◽  
Combustion Process ◽  
Energy Transition ◽  
Combustion Efficiency ◽  
Review Article ◽  
Cavitation Phenomenon ◽  
Heat Engines ◽  
High Speeds

Concerning the problem of wanting the performance of heat engines used in the automotive, aeronautics, and aerospace industries, researchers and engineers are working on various possibilities for improving combustion efficiency, including the reduction of gases such as CO, NOx, and SOx. Such improvements would also help reduce greenhouse gases. For this, research and development has focused on one factor that has a significant impact on the performance of these engines: the phenomenon of cavitation. In fact, most high-performance heat engines are fitted with a high-speed fuel supply system. These high speeds lead to the formation of the phenomenon of cavitation generating instabilities in the flow and subsequently causing disturbances in the combustion process and in the efficiency of the engine. In this review article, it is a question of making a state-of-the-art review on the various studies which have dealt with the characterization of the phenomenon of cavitation and addressing the possible means that can be put in place to reduce its effects. The bibliographic study was carried out based on five editors who are very involved in this theme. From the census carried out, it has been shown that there are many works which deal with the means of optimization that must be implemented in order to fight against the phenomenon of cavitation. Among these solutions, there is the optimization of the geometry of the injector in which the fuel flows and there is the type of fuel used. Indeed, it is shown that the use of a biofuel, which, by its higher viscosity, decreases the effects of cavitation. Most of these jobs are performed under cold fluidic conditions; however, there is little or no work that directly addresses the effect of cavitation on the combustion process. Consequently, this review article highlights the importance of carrying out research work, with the objective of characterizing the effect of cavitation on the combustion process and the need to use a biofuel as an inhibitor solution on the cavitation phenomenon and as a means of energy transition.

scholarly journals Design and Implementation of DDS Module on FPGA

2021 ◽  
Vol 10 (2) ◽  
pp. 1296-1299
Keyword(s):  
High Performance ◽  
Frequency Conversion ◽  
Sine Wave ◽  
Direct Digital Synthesis ◽  
Output Frequency ◽  
Gate Arrays ◽  
Construction Scheme ◽  
Field Programmable ◽  
Digital Synthesis ◽  
Programmable Gate Arrays

he paper concerns the construction scheme of Direct Digital Synthesis (DDS) generator based on widely developed Field Programmable Gate Arrays (FPGA) technology. based on (DDS) it generates sine wave that frequency and phase is manageable is designed with direct digital synthesis(DDS) technology. It is showed that the design based on FPGA with DDS is dependable and practicable. The output wave by test reaches the essential aims, easy control and high performance. The DDS produce sinusoidal signal owns the features of modest circuit, easy to be measured, unchanging performance, high frequency conversion speed and fine accuracy etc. And its output frequency falls within the range of 0Hz ~ 150KHz with 5 Hz of steps

scholarly journals Development of a High-Speed Digitizer to Time Resolve Nanosecond Fluorescence Pulses

2012 ◽  
Vol 10 (2) ◽  
Author(s):  
E. Moreno-García ◽  
R. Galicia-Mejía ◽  
D. Jiménez-Olarte ◽  
J. M. de la Rosa Vázquez ◽  
S. Stolik-Isakina
Keyword(s):  
Time Domain ◽  
Digital Signal Processor ◽  
High Speed ◽  
High Performance ◽  
Input Pulse ◽  
Control Program ◽  
Sampling Technique ◽  
Digital Signal ◽  
Time Resolved ◽  
The Time Domain

The development of a high-speed digitizer system to measure time-domain voltage pulses in nanoseconds range is presented in this work. The digitizer design includes a high performance digital signal processor, a high-bandwidth analog-to-digital converter of flash-type, a set of delay lines, and a computer to achieve the time-domain measurements. A program running on the processor applies a time-equivalent sampling technique to acquire the input pulse. The processor communicates with the computer via a serial port RS-232 to receive commands and to transmit data. A control program written in LabVIEW 7.1 starts an acquisition routine in the processor. The program reads data from processor point by point in each occurrence of the signal, and plots each point to recover the time-resolved input pulse after n occurrences. The developed prototype is applied to measure fluorescence pulses from a homemade spectrometer. For this application, the LabVIEW program was improved to control the spectrometer, and to register and plot time-resolved fluorescence pulses produced by a substance. The developed digitizer has 750 MHz of analog input bandwidth, and it is able to resolve 2 ns rise-time pulses with 150 ps of resolution and a temporal error of 2.6 percent.

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