A 75dB Programmable Gain Amplifier for Dual Mode Wireless Receivers

2012 ◽  
Vol 229-231 ◽  
pp. 1609-1613
Author(s):  
Xiang Ning Fan ◽  
Kuan Bao ◽  
Da Chen ◽  
Liang Yi Ma
Keyword(s):  
Supply Voltage ◽  
Cmos Technology ◽  
Dual Mode ◽  
Peak Voltage ◽  
Dc Offset ◽  
Variable Gain ◽  
Gain Error ◽  
Programmable Gain Amplifier ◽  
Programmable Gain ◽  
Gain Stage

In this paper, a programmable gain amplifier (PGA) is designed and implemented for GPS/Galileo and WCDMA dual mode receiver using TSMC 0.18μm CMOS technology. The 0-75dB variable gain range is obtained by cascading a 0-15dB variable gain stage and four 15dB fixed gain stages. An open-loop structured fully-differential amplifier with source feedback resistor is adopted in basic gain stage. Variation of gain is achieved by switch-controlled output resistor network. Gm-boost structure is used in main amplifier. A DC-offset canceller circuit using DC negative feedback technique is proposed to eliminate the DC-offset of the PGA. Post-simulation shows that the PGA has 0-75dB variable gain range, 1dB gain resolution and less than 0.3dB gain error; the minimum DC attenuation is about 15dB over the whole gain range; -3dB bandwidth at the maximum gain configuration is about 15MHz; differential output peak to peak voltage is greater than 1V; and the entire circuit consumes about 3.6mA current under 1.8V supply voltage.

scholarly journals EMG extractor and blink detection for human health monitoring

2018 ◽  
Vol 7 (2) ◽  
pp. 706
Author(s):  
Aanchal Jha ◽  
M. Ganesh Lakshamana Kumar
Keyword(s):  
Human Health ◽  
Health Monitoring ◽  
Biomedical Applications ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Emg Signal ◽  
Blink Detection ◽  
Programmable Gain Amplifier ◽  
Programmable Gain ◽  
Chebyshev Filter

In this paper we have proposed noise free EMG extractor for biomedical applications and also provide method for detecting blink signal. EMG signal is applied to preamplifier followed by Chebyshev filter and programmable gain amplifier further this processed EMG signal is applied to comparator to detect the blink. This topology is designed in UMC 180nm CMOS technology. Amplifier with gain of 81.155 dB and CMRR of 155.197 dB is designed. Preamplifier gain of 32.1244 dB with CMRR of 76.0743 dB which leads to common mode cancellation at priliminary stage. It also provide input referred noise ranges from 90 to 101.8636 µ V/sqrt(Hz) to reduce the noise for overall system. 4th order Chebyshev filter provides filtering with slope of -80 dB/decade with leads to reduce the unwanted signals. Filtered EMG signal is applied to programmable gain amplifier where gain ranges from 0 to 23 dB.It consumes power of 0.3µ W at 1V supply voltage.

Noise Analysis and Optimization of Programmable Gain Amplifier with DC Offset Cancelation

2015 ◽  
Vol 35 (3) ◽  
pp. 753-770 ◽  
Author(s):  
Li Ma ◽  
Zhigong Wang ◽  
Jian Xu ◽  
Rong Wang ◽  
Najam Muhammad Amin
Keyword(s):  
Noise Analysis ◽  
Dc Offset ◽  
Programmable Gain Amplifier ◽  
Programmable Gain

Analysis and Design of a Linear Digital Programmable Gain Amplifier in a 0.13 µm SiGe BiCMOS technology

Frequenz ◽  
2017 ◽  
Vol 71 (3-4) ◽  
Author(s):  
Xuan-Quang Du ◽  
Anselm Knobloch ◽  
Markus Grözing ◽  
Matthias Buck ◽  
Manfred Berroth
Keyword(s):  
Harmonic Distortion ◽  
Gain Control ◽  
Step Size ◽  
Analysis And Design ◽  
Fully Differential ◽  
Gain Error ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Programmable Gain Amplifier ◽  
Programmable Gain

AbstractThis paper presents the analysis and the design of a fully-differential digital programmable gain amplifier (PGA) in a 0.13 µm BiCMOS technology. The PGA has a gain control range of 31 dB with 1 dB gain step size and consumes 284 mW from a 3.6 V power supply. At a maximum gain of 25 dB, the PGA exhibits a 3-dB bandwidth of 10.1 GHz. The measured gain error for all 32 possible gain settings is between –0.19/+0.46 dB at 1 GHz. Up to 13 GHz the third harmonic distortion

scholarly journals Design of a Programmable Gain Amplifier (PGA) for Bluetooth Low Energy (BLE) in 0.13 um CMOS

2020 ◽  
Vol 15 (1) ◽  
pp. 1-9
Author(s):  
Isaías De Sousa Barbosa Júnior ◽  
Raimundo Carlos Silverio Freire ◽  
Edelson Da Silva Procopio Venuto
Keyword(s):  
Supply Voltage ◽  
Low Energy ◽  
Common Source ◽  
Resistive Load ◽  
Bluetooth Low Energy ◽  
Analog To Digital ◽  
Low Area ◽  
Programmable Gain Amplifier ◽  
Minimum Bandwidth ◽  
Programmable Gain

Programmable Gain Amplifiers (PGA's) are circuits capable of conveniently changing their gain to address various levels of amplification. Knowing this, the topology proposed in this work takes a source degenerated first stage, a common-source with resistive load second stage, and a gm boosting circuit interface to realize a PGA that has low power consumption and low area. The design developed was able to achieve a maximum power dissipation of 103.1 uW, a minimum bandwidth of 5.59 MHz, a maximum noise of 32.01 nV/sqrt(Hz), and a gain range of 2.31 - 19.84 dB. Each differential output of the circuit is loaded with 700 fF, which is the estimated load for the hypothetical following block, the Analog-to-Digital Converter (ADC). Furthermore, the supply voltage of the circuit is 1 V and the design was undertaken on Global Foundrie's 130 nm technology. The phase margin of the core circuit is no greater than 100.3˚  and no less than 49˚  . The circuit which design is described in this work is intended to be within the receiver (RX) sub-domain of a Bluetooth Low-Energy (BLE) system, which finds applications on the IoT and healthcare industries, for instance.

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