High-Performance Real-Time Bus in Parallel Processing System

2013 ◽  
Vol 278-280 ◽  
pp. 1043-1046
Author(s):  
Xin Cheng ◽  
Hua Chun Wu
Keyword(s):  
Parallel Processing ◽  
Real Time ◽  
Data Transmission ◽  
High Performance ◽  
Data Exchange ◽  
Processing System ◽  
Distributed Shared Memory ◽  
Transmission Model ◽  
Time Signal ◽  
Complexity Of Algorithms

Rapid increases in the complexity of algorithms for real-time signal processing applications have made multi-processors parallel processing technology needed. This paper proposes a design of high-performance real-time bus (RTB), based on which distributed shared memory (DSM) mechanism is established to implement data exchange among multiple processors. Adopting DSM mechanism can reduce the software overhead and improve data processing performance significantly. Definition and implementation details of RTB and data transmission model are discussed. Experimental results show the stable data transmission bandwidth is achieved with performance not affected by the increasing number of processors.

scholarly journals Design and Implementation ofReal-time Electrical Stimulation Artifact Suppression based on STM32

2021 ◽  
Vol 12 (5) ◽  
pp. 424-427
Author(s):  
Sangsoo Park, Hojun Yeom
Keyword(s):  
Central Nervous System ◽  
Nervous System ◽  
Electrical Stimulation ◽  
Embedded System ◽  
Muscle Contraction ◽  
Real Time ◽  
High Performance ◽  
Floating Point ◽  
Time Signal ◽  
Central Nervous System Damage

A biosignal is used as a control signal for electrical stimulation to restore weakened muscle function due to damage to the central nervous system. In patients with central nervous system damage, sufficient muscle contraction does not occur spontaneously. In this case, applying electrical stimulation can cause normal muscle contraction. However, it is necessary to remove the electrical stimulation artifact caused by the electrical stimulation. This paper describes a system design that removes electrical stimulation artifact in real time using a Cortex-M4-based STM32F processor. The STM32F is a very advantageous MCU for such DSPs, especially because it has a built-in floating point operator. Using STM32F's various high-performance peripherals (12-bit parallel ADC and 12-bit DAC, UART, Timer), an optimized embedded system was implemented.In this paper, the simulated and real-time results were compared and evaluated with the designed fir filter. In addition, the performance of the filter was evaluated through frequency analysis. As a result, it was verified that a high-performance 32-bit STM32F with floating point calculator and various peripherals is suitable for real-time signal processing

Petersen-star networks modeled by optical transpose interconnection system

2021 ◽  
Vol 17 (11) ◽  
pp. 155014772110331
Author(s):  
Jung-hyun Seo ◽  
HyeongOk Lee
Keyword(s):  
Parallel Processing ◽  
Optical Communication ◽  
Time Complexity ◽  
High Performance ◽  
Electronic Communication ◽  
Interconnection Network ◽  
Processing System ◽  
Factor Graph ◽  
Star Network ◽  
Network Cost

One method to create a high-performance computer is to use parallel processing to connect multiple computers. The structure of the parallel processing system is represented as an interconnection network. Traditionally, the communication links that connect the nodes in the interconnection network use electricity. With the advent of optical communication, however, optical transpose interconnection system networks have emerged, which combine the advantages of electronic communication and optical communication. Optical transpose interconnection system networks use electronic communication for relatively short distances and optical communication for long distances. Regardless of whether the interconnection network uses electronic communication or optical communication, network cost is an important factor among the various measures used for the evaluation of networks. In this article, we first propose a novel optical transpose interconnection system–Petersen-star network with a small network cost and analyze its basic topological properties. Optical transpose interconnection system–Petersen-star network is an undirected graph where the factor graph is Petersen-star network. OTIS–PSN n has the number of nodes 102n, degree n+3, and diameter 6 n − 1. Second, we compare the network cost between optical transpose interconnection system–Petersen-star network and other optical transpose interconnection system networks. Finally, we propose a routing algorithm with a time complexity of 6 n − 1 and a one-to-all broadcasting algorithm with a time complexity of 2 n − 1.

Reconfigurable distributed real-time processing for multi-robot control: Design, implementation and experimentation

Robotica ◽  
2004 ◽  
Vol 22 (6) ◽  
pp. 661-679 ◽  
Author(s):  
J. Z. Pan ◽  
R. V. Patel
Keyword(s):  
Real Time ◽  
Information Exchange ◽  
Robot Control ◽  
Data Exchange ◽  
Processing System ◽  
System Level ◽  
Layered System ◽  
Test Bed ◽  
Design And Implementation ◽  
Multi Robot

Sophisticated robotic applications require systems to be reconfigurable at the system level. Aiming at this requirement, this paper presents the design and implementation of a software architecture for a reconfigurable real-time multi-processing system for multi-robot control. The system is partitioned into loosely coupled function units and the data modules manipulated by the function units. Modularized and unified structures of the sub-controllers and controller processes are designed and constructed. All the controller processes run autonomously and intra-sub-controller information exchange is realized by shared data modules that serve as a data repository in the sub-controller. The dynamic data-management processes are responsible for data exchange among sub-controllers and across the computer network. Among sub-controllers there is no explicit temporal synchronization and the data dependencies are maintained by using datum-based synchronization. The hardware driver is constructed as a two-layered system to facilitate adaptation to various robotic hardware systems. A series of effective schemes for software fault detection, fault anticipation and fault termination are accomplished to improve run-time safety. The system is implemented cost-effectively on a QNX real-time operating system (RTOS) based system with a complete PC architecture, and experimentally validated successfully on an experimental dual-arm test-bed. The results indicate that the architectural design and implementation are well suited for advanced application tasks.

Sign in / Sign up

Export Citation Format

Share Document