An Improved Dynamic Trust Model for Distributed System

2014 ◽  
Vol 1046 ◽  
pp. 500-503
Author(s):  
Chong Yang Ye ◽  
Yi Zhuang

The parallel, sharing and high speed distributed system has become the mainstream of current system architecture, the characteristics of uncentralized management makes more and more people take flexible operations. However, as the nodes in the system are not bound by a central server and resource sharing is a node’s voluntary behavior, the traditional centralized mechanism is not suitable for large-scale distributed system. Aiming at this problem, this paper proposes an improved dynamic trust model for distributed system (IDTrust) to quantify and evaluate the credible degree between nodes. The analysis and simulation results show that the effectiveness of contain malicious nodes and the security aspects of IDTrust are superior to those of current typical methods.

2013 ◽  
Vol 397-400 ◽  
pp. 1949-1953 ◽  
Author(s):  
Feng Li ◽  
Ya Li Si

Trust mechanism has been identified as one of key areas in the field of Internet security. Our objective in this paper is to develop a dynamic trust evaluation model for Internet computing. The proposed scheme divides the recommendation trust into the direct recommendation trust and the indirect recommendation trust, and considers variety of factors to calculate the two types of recommendation trust degree. Simulation results show that, compared to the existing trust model, the model can effectively improve the accuracy of trust evaluation, and provide a better capacity of resisting malicious entities.


2004 ◽  
Vol 14 (03) ◽  
pp. 646-651 ◽  
Author(s):  
STEVEN EUGENE TURNER ◽  
DAVID E. KOTECKI

High-speed accumulators are frequently used as a benchmark of the high-speed performance and ability to yield large scale circuits in InP double hetereojunction bipolar (DHBT) processes. In previous work, we reported test results of an InP DHBT 4-bit accumulator with 624 transistors operating at 41 GHz clock frequency with a power consumption of 4.1W. In this work, we report on modifications that allow the circuit to operate at a lower supply voltage and a corresponding lower power consumption. Simulation results for this modification indicate that a 16% power reduction can be obtained, while maintaining a high-speed operating frequency of 40 GHz.


2020 ◽  
Vol 2020 (3) ◽  
pp. 304-326
Author(s):  
Alexander Bajic ◽  
Georg T. Becker

AbstractThe Internet infrastructure has not been built with security or privacy in mind. As a result, an adversary who has control over a single Autonomous System can set-up mass surveillance systems to gather meta data by passively collecting the headers of the messages they route. To solve this problem, lightweight anonymous routing protocols such as LAP, DOVETAIL and most recently PHI have been proposed which are efficient enough to be deployed in a large scale infrastructure such as the Internet. In this paper we take a closer look at PHI and introduce several de-anonymization attacks malicious nodes can perform to reduce the sender and receiver anonymity. As a direct consequence of this analysis we propose a new protocol called dependable PHI (dPHI). The security analysis of dPHI includes a detailed quantitative anonymity analysis that compares dPHI with PHI, LAP and HORNET. Together with the performance analysis, this allows for a good comparison of trade-offs for these anonymity protocols.


2006 ◽  
Vol 15 (01) ◽  
pp. 129-144 ◽  
Author(s):  
SHUGANG WEI ◽  
KENSUKE SHIMIZU

In this paper, a new three-operand modulo (2p ± 1) addition is implemented by performing a carry-save addition and a two-operand modular addition based on the p-digit radix-two signed-digit (SD) number system. Thus, the delay time of the three-operand modular adder is independent of the word length of the operands. A modulo (2p ± 1) multiplier is constructed as a ternary tree of the three-operand modular SD adders, and the modular multiplication time is proportional to log 3 p. When a serial modular multiplier is constructed using the three-operand modular SD adder, two modular partial products can be added to the sum at the same time. Two kinds of Booth recoding methods are also proposed to reduce the partial products from p to p/2. Therefore, the performance of a parallel modular multiplier can be modified by reducing half of the modular SD adders in the adder tree. For a serial modular multiplication, two partial products are generated from two Booth recoders and added to the sum by using one three-operand modular SD adder, so that the speed of the modular multiplication is three times as fast as the speed without using the three-operand modular SD adder and the Booth recoding method. A very large-scale integration (VLSI) implementation method by VHDL is also discussed. The design and simulation results show that high-speed modular multipliers can be obtained by the algorithms presented.


2021 ◽  
Vol 2021 ◽  
pp. 1-12
Author(s):  
Peng Wu ◽  
Ning Xiong ◽  
Jiqiang Liu ◽  
Liujia Huang ◽  
Zhuoya Ju ◽  
...  

Decentralized power systems are commonly used in high-speed trains. However, many parameters in decentralized power systems are uncertain and inevitably have errors. We present a reasoning method based on the interval numbers for decentralized power systems in high-speed trains. Uncertain parameters and their unavoidable errors are quantitatively described by interval numbers. We also define generalized linear equations with interval numbers (LAIs), which can be used to describe the movement of the train. Furthermore, it is proven that the zero sets of LAIs are convex. Therefore, the inside of the fault-tolerance area can be formed by their vertexes and edges and represented by linear inequalities. Consequently, we can judge whether the system is working properly by verifying that the current system state is in the fault-tolerance area. Finally, a fault-tolerance area is obtained, which can be determined by linear equations with an interval number, and we test the correctness of the fault-tolerance area through large-scale random test cases.


2019 ◽  
Vol 16 (7) ◽  
pp. 174-194 ◽  
Author(s):  
Weijin Jiang ◽  
Yang Wang ◽  
Yirong Jiang ◽  
Jiahui Chen ◽  
Yuhui Xu ◽  
...  

Sign in / Sign up

Export Citation Format

Share Document